diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-03-12 18:32:35 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2024-03-19 09:56:49 +0000 |
| commit | 8061957cc12769714e7041093c065c6d6d212249 (patch) | |
| tree | 40379a2ac52cd0ab971852394d9d01cf1181728e /src/soc/intel/xeon_sp/spr | |
| parent | d425e881e339e8f92c48237d1e212275c5a7cdc3 (diff) | |
soc/intel/xeon_sp: Initial support for PCI multi segment groups
Add PCI enumeration support by reading the PCIeSegment reported in the
FSP HOB and add it when creating the PCI domain for each stack.
The PCI enumeration will be able to scan the additional PCI segment
groups and properly handle those devices.
TEST=Booted on ibm/sbp1 with multiple PCI segment groups enabled
to ubuntu 22.04.
TEST=intel/archercity CRB
Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79878
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/ioat.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 2e3baa3cb0..cdf98347f6 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -34,7 +34,7 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons const unsigned int bus_base, const unsigned int bus_limit, const resource_t mem32_base, const resource_t mem32_limit, const resource_t mem64_base, const resource_t mem64_limit, - const char *prefix) + const char *prefix, const size_t pci_segment_group) { union xeon_domain_path new_path = { .domain_path = dp.domain_path @@ -58,6 +58,7 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons bus->secondary = bus_base; bus->subordinate = bus->secondary; bus->max_subordinate = bus_limit; + bus->segment_group = pci_segment_group; unsigned int index = 0; @@ -78,7 +79,10 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons } } -void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *const bus, const STACK_RES *const sr) +void soc_create_ioat_domains(const union xeon_domain_path path, + struct bus *const bus, + const STACK_RES *const sr, + const size_t pci_segment_group) { if (sr->BusLimit < sr->BusBase + HQM_BUS_OFFSET + HQM_RESERVED_BUS) { printk(BIOS_WARNING, @@ -104,7 +108,7 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons bus_base = sr->BusBase + CPM_BUS_OFFSET; bus_limit = bus_base + CPM_RESERVED_BUS; create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, - DOMAIN_TYPE_CPM0); + DOMAIN_TYPE_CPM0, pci_segment_group); /* HQM0 */ mem64_base = mem64_limit + 1; @@ -112,7 +116,7 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons bus_base = sr->BusBase + HQM_BUS_OFFSET; bus_limit = bus_base + HQM_RESERVED_BUS; create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, - DOMAIN_TYPE_HQM0); + DOMAIN_TYPE_HQM0, pci_segment_group); /* CPM1 (optional) */ mem64_base = mem64_limit + 1; @@ -121,7 +125,7 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons bus_limit = bus_base + CPM_RESERVED_BUS; if (bus_limit <= sr->BusLimit) create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, - DOMAIN_TYPE_CPM1); + DOMAIN_TYPE_CPM1, pci_segment_group); /* HQM1 (optional) */ mem64_base = mem64_limit + 1; @@ -130,7 +134,7 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons bus_limit = bus_base + HQM_RESERVED_BUS; if (bus_limit <= sr->BusLimit) create_ioat_domain(path, bus, bus_base, bus_limit, -1, 0, mem64_base, mem64_limit, - DOMAIN_TYPE_HQM1); + DOMAIN_TYPE_HQM1, pci_segment_group); /* DINO */ mem64_base = mem64_limit + 1; @@ -138,5 +142,5 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons bus_base = sr->BusBase; bus_limit = bus_base; create_ioat_domain(path, bus, bus_base, bus_limit, sr->PciResourceMem32Base, sr->PciResourceMem32Limit, - mem64_base, mem64_limit, DOMAIN_TYPE_DINO); + mem64_base, mem64_limit, DOMAIN_TYPE_DINO, pci_segment_group); } |