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authorJincheng Li <jincheng.li@intel.com>2024-03-13 15:06:26 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-03-26 10:10:48 +0000
commit31998020458af821cb61d0000ee2cbd0293958f6 (patch)
tree280829f2d75b7c2582f4d5ad5308e7fdebbcd635 /src/soc/intel/xeon_sp/spr
parente17113a3f3f3d6ccf5f79bea7c405e983860bc52 (diff)
soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms
DDR support codes across generations are similar. Share the codes to improve code reuse. TEST=intel/archercity CRB Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr')
-rw-r--r--src/soc/intel/xeon_sp/spr/Makefile.mk2
-rw-r--r--src/soc/intel/xeon_sp/spr/ddr.c93
-rw-r--r--src/soc/intel/xeon_sp/spr/include/soc/ddr.h57
-rw-r--r--src/soc/intel/xeon_sp/spr/romstage.c5
4 files changed, 1 insertions, 156 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk
index fc8ab1713d..d999f30661 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/spr/Makefile.mk
@@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/mtrr
subdirs-y += ../../../../cpu/x86/tsc
subdirs-y += ../../../../cpu/intel/microcode
-romstage-y += romstage.c soc_util.c ddr.c
+romstage-y += romstage.c soc_util.c
romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/soc/intel/xeon_sp/spr/ddr.c b/src/soc/intel/xeon_sp/spr/ddr.c
deleted file mode 100644
index ff61a7e8a4..0000000000
--- a/src/soc/intel/xeon_sp/spr/ddr.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <soc/ddr.h>
-
-unsigned int get_ddr_millivolt(unsigned int ddr_voltage)
-{
- switch (ddr_voltage) {
- case SPD_VDD_DDR4:
- return 1200;
- case SPD_VDD_DDR5:
- return 1100;
- default:
- return 0;
- }
-}
-
-unsigned int get_max_memory_speed(unsigned int commonTck)
-{
- if (commonTck <= DDR_8400_TCK_MIN)
- return 8400;
- else if (commonTck <= DDR_7600_TCK_MIN)
- return 7600;
- else if (commonTck <= DDR_7200_TCK_MIN)
- return 7200;
- else if (commonTck <= DDR_6800_TCK_MIN)
- return 6800;
- else if (commonTck <= DDR_6400_TCK_MIN)
- return 6400;
- else if (commonTck <= DDR_6000_TCK_MIN)
- return 6000;
- else if (commonTck <= DDR_5600_TCK_MIN)
- return 5600;
- else if (commonTck <= DDR_5200_TCK_MIN)
- return 5200;
- else if (commonTck <= DDR_4800_TCK_MIN)
- return 4800;
- else if (commonTck <= DDR_4400_TCK_MIN)
- return 4400;
- else if (commonTck <= DDR_4266_TCK_MIN)
- return 4266;
- else if (commonTck <= DDR_4200_TCK_MIN)
- return 4200;
- else if (commonTck <= DDR_4000_TCK_MIN)
- return 4000;
- else if (commonTck <= DDR_3800_TCK_MIN)
- return 3800;
- else if (commonTck <= DDR_3733_TCK_MIN)
- return 3733;
- else if (commonTck <= DDR_3600_TCK_MIN)
- return 3600;
- else if (commonTck <= DDR_3466_TCK_MIN)
- return 3466;
- else if (commonTck <= DDR_3400_TCK_MIN)
- return 3400;
- else if (commonTck <= DDR_3200_TCK_MIN)
- return 3200;
- else if (commonTck <= DDR_3000_TCK_MIN)
- return 3000;
- else if (commonTck <= DDR_2933_TCK_MIN)
- return 2933;
- else if (commonTck <= DDR_2800_TCK_MIN)
- return 2800;
- else if (commonTck <= DDR_2666_TCK_MIN)
- return 2666;
- else if (commonTck <= DDR_2600_TCK_MIN)
- return 2600;
- else if (commonTck <= DDR_2400_TCK_MIN)
- return 2400;
- else if (commonTck <= DDR_2200_TCK_MIN)
- return 2200;
- else if (commonTck <= DDR_2133_TCK_MIN)
- return 2133;
- else if (commonTck <= DDR_2000_TCK_MIN)
- return 2000;
- else if (commonTck <= DDR_1866_TCK_MIN)
- return 1866;
- else if (commonTck <= DDR_1800_TCK_MIN)
- return 1800;
- else if (commonTck <= DDR_1600_TCK_MIN)
- return 1600;
- else if (commonTck <= DDR_1400_TCK_MIN)
- return 1400;
- else if (commonTck <= DDR_1333_TCK_MIN)
- return 1333;
- else if (commonTck <= DDR_1200_TCK_MIN)
- return 1200;
- else if (commonTck <= DDR_1066_TCK_MIN)
- return 1066;
- else if (commonTck <= DDR_1000_TCK_MIN)
- return 1000;
- else
- return 800;
-}
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/ddr.h b/src/soc/intel/xeon_sp/spr/include/soc/ddr.h
deleted file mode 100644
index f2dc5c8998..0000000000
--- a/src/soc/intel/xeon_sp/spr/include/soc/ddr.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _SPR_DDR_H_
-#define _SPR_DDR_H_
-
-#include <types.h>
-
-/* SPD Byte 11: Module Nominal Voltage
- * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */
-#define SPD_VDD_DDR4 3
-#define SPD_VDD_DDR5 0
-#define SPD_TYPE_DDR5 0x12
-
-/* DDR_*_TCK_MIN are in picoseconds */
-#define DDR_1000_TCK_MIN 2000
-#define DDR_1066_TCK_MIN 1875
-#define DDR_1200_TCK_MIN 1667
-#define DDR_1333_TCK_MIN 1500
-#define DDR_1400_TCK_MIN 1429
-#define DDR_1600_TCK_MIN 1250
-#define DDR_1800_TCK_MIN 1110
-#define DDR_1866_TCK_MIN 1071
-#define DDR_2000_TCK_MIN 1000
-#define DDR_2133_TCK_MIN 938
-#define DDR_2200_TCK_MIN 909
-#define DDR_2400_TCK_MIN 833
-#define DDR_2600_TCK_MIN 769
-#define DDR_2666_TCK_MIN 750
-#define DDR_2800_TCK_MIN 714
-#define DDR_2933_TCK_MIN 682
-#define DDR_3000_TCK_MIN 667
-#define DDR_3200_TCK_MIN 625
-#define DDR_3400_TCK_MIN 589
-#define DDR_3466_TCK_MIN 577
-#define DDR_3600_TCK_MIN 556
-#define DDR_3733_TCK_MIN 536
-#define DDR_3800_TCK_MIN 527
-#define DDR_4000_TCK_MIN 500
-#define DDR_4200_TCK_MIN 477
-#define DDR_4266_TCK_MIN 469
-#define DDR_4400_TCK_MIN 455
-#define DDR_4800_TCK_MIN 417
-#define DDR_5200_TCK_MIN 385
-#define DDR_5600_TCK_MIN 358
-#define DDR_6000_TCK_MIN 334
-#define DDR_6400_TCK_MIN 313
-#define DDR_6800_TCK_MIN 295
-#define DDR_7200_TCK_MIN 278
-#define DDR_7600_TCK_MIN 264
-#define DDR_8000_TCK_MIN 250
-#define DDR_8400_TCK_MIN 239
-
-unsigned int get_max_memory_speed(unsigned int commonTck);
-unsigned int get_ddr_millivolt(unsigned int ddr_voltage);
-bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot);
-
-#endif /* _SPR_DDR_H_ */
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 74976b362e..3b38828492 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -32,11 +32,6 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
/* Default weak implementation */
}
-bool __weak mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
-{
- return false;
-}
-
/*
* Search from VPD_RW first then VPD_RO for UPD config variables,
* overwrites them from VPD if it's found.