diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-25 11:37:27 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-19 09:53:02 +0000 |
| commit | 3ed903fda9cb9b7237067f301d1efdb297a05a24 (patch) | |
| tree | d5dd7beda731aea7ddbd6a80c7c151b5d1d38107 /src/soc/intel/xeon_sp/spr/chipset.cb | |
| parent | 15fc45982b9b8303978ab87ea6c93d423834e6e8 (diff) | |
soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code
It implements SPR ramstage including silicon initialization, MSR
programming, MP init and certain registers locking before booting
to payload.
Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr/chipset.cb')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/chipset.cb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/spr/chipset.cb b/src/soc/intel/xeon_sp/spr/chipset.cb index efc8637a56..9a913d96dc 100644 --- a/src/soc/intel/xeon_sp/spr/chipset.cb +++ b/src/soc/intel/xeon_sp/spr/chipset.cb @@ -32,9 +32,7 @@ chip soc/intel/xeon_sp/spr register "gen2_dec" = "0x000c0ca1" # IPMI KCS register "cstate_states" = "CSTATES_C1C6" - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Intel device 09a2: Memory Map/Intel VT-d device pci 00.1 on end # Intel device 09a4: Mesh to IAL |