soc/intel/xeon_sp/spr: Add ACPI support for Sapphire Rapids

Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests.
The code was written from scratch because there are Xeon-SP specific
implementation especially Integrated Input/Output (IIO).

Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

9 files changed, 1819 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
new file mode 100644
index 0000000000..299247f9a1
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define _IIO_DEVICE_NAME(str, skt, stk)     str##skt##stk
+#define IIO_DEVICE_NAME(str, skt, stk)      _IIO_DEVICE_NAME(str, skt, stk)
+#define IIO_RESOURCE_NAME(res, str, skt, stk)      res##str##skt##stk
+
+#define STR(s)  #s
+#define _IIO_DEVICE_UID(str, skt, stk)      STR(str##skt##stk)
+#define IIO_DEVICE_UID(str, skt, stk)       _IIO_DEVICE_UID(str, skt, stk)
+
+Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK))
+{
+	Name (_HID, "ACPI0017") /* CXL */
+	Name (_CID, Package (0x02)
+	{
+		EisaId ("PNP0A08") /* PCI Express Bus */,
+		EisaId ("PNP0A03") /* PCI Bus */
+	})
+	Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK))
+	External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK))
+	Method (_STA, 0, NotSerialized)  // _STA: Status
+	{
+		Return (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK))
+	}
+	Method (_PRT, 0, NotSerialized)
+	{
+		Return (\_SB.PRTID)
+	}
+	External (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
+	Method (_CRS, 0, NotSerialized)
+	{
+		Return (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
+	}
+	Name (SUPP, 0x00) // PCI _OSC Support Field Value
+	Name (CTRL, 0x00) // PCI _OSC Control Field Value
+	Name (SUPC, 0x00) // CXL _OSC Support Field Value
+	Name (CTRC, 0x00) // CXL _OSC Control Field Value
+	Name (_PXM, 0x00)  /* _PXM: Device Proximity */
+	Method (_OSC, 4, NotSerialized)
+	{
+		CreateDWordField (Arg3, 0x00, CDW1)
+		If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */
+			|| Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc"))
+			/* CXL */
+		{
+			CreateDWordField (Arg3, 0x04, CDW2)
+			If (Arg2 > 0x02)
+			{
+				CreateDWordField (Arg3, 0x08, CDW3)
+				CreateDWordField (Arg3, 0x0C, CDW4)
+				CreateDWordField (Arg3, 0x10, CDW5)
+			}
+			SUPP = CDW2
+			CTRL = CDW3
+			SUPC = CDW4
+			CTRC = CDW5
+			If (SUPP & 0x16 != 0x16)
+			{
+				CTRL &= 0x1E
+				Sleep (0x03E8)
+			}
+			/* Never allow SHPC (no SHPC controller in system) */
+			CTRL &= 0x1D
+			/* Disable Native PCIe AER handling from OS */
+			CTRL &= 0x17
+			If (Arg1 != 1) /* unknown revision */
+			{
+				CDW1 |= 0x08
+			}
+			If (CDW3 != CTRL) /* capabilities bits were masked */
+			{
+				CDW1 |= 0x10
+			}
+			CDW3 = CTRL
+			CDW5 = CTRC
+			Return (Arg3)
+		}
+		Else
+		{
+			/* indicate unrecognized UUID */
+			CDW1 |= 0x04
+			IO80 = 0xEE
+			Return (Arg3)
+		}
+	}
+}
diff --git a/src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
new file mode 100644
index 0000000000..606c074659
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#undef PRTID
+#define PRTID      AR12
+
+#undef DEVPREFIX
+#define DEVPREFIX  DI
+#undef RESPREFIX
+#define RESPREFIX  DT
+#include "pci_resource.asl"
+
+#undef DEVPREFIX
+#define DEVPREFIX  PM
+#undef RESPREFIX
+#define RESPREFIX  MT
+#include "pci_resource.asl"
+
+#undef DEVPREFIX
+#define DEVPREFIX  HQ
+#undef RESPREFIX
+#define RESPREFIX  HT
+#include "pci_resource.asl"
+
+#undef DEVPREFIX
+#define DEVPREFIX  PN
+#undef RESPREFIX
+#define RESPREFIX  MU
+#include "pci_resource.asl"
+
+#undef DEVPREFIX
+#define DEVPREFIX  HR
+#undef RESPREFIX
+#define RESPREFIX  HU
+#include "pci_resource.asl"
diff --git a/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
new file mode 100644
index 0000000000..bf70bbc5b4
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* ***** PCI Stacks **** */
+#undef DEVPREFIX
+#define DEVPREFIX  PC
+#undef RESPREFIX
+#define RESPREFIX  PT
+#undef STPREFIX
+#define STPREFIX   ST
+
+#undef PRTID
+#define PRTID      AR00
+#undef STACK
+#define STACK 0
+#include "pci_resource.asl"
+
+#undef PRTID
+#define PRTID      AR01
+#undef STACK
+#define STACK 1
+#include "pci_resource.asl"
+
+#undef STACK
+#define STACK 2
+#include "pci_resource.asl"
+
+#undef STACK
+#define STACK 3
+#include "pci_resource.asl"
+
+#undef STACK
+#define STACK 4
+#include "pci_resource.asl"
+
+#undef STACK
+#define STACK 5
+#include "pci_resource.asl"
+
+/* ***** CXL Stacks **** */
+#undef DEVPREFIX
+#define DEVPREFIX  CX
+#undef RESPREFIX
+#define RESPREFIX  CT
+
+#undef STACK
+#define STACK 1
+#include "cxl_resource.asl"
+
+#undef STACK
+#define STACK 2
+#include "cxl_resource.asl"
+
+#undef STACK
+#define STACK 3
+#include "cxl_resource.asl"
+
+#undef STACK
+#define STACK 4
+#include "cxl_resource.asl"
+
+#undef STACK
+#define STACK 5
+#include "cxl_resource.asl"
+
+/* ***** DINO,CPM,HQM Stacks **** */
+#undef STACK
+#define STACK 8
+#include "dino_resource.asl"
+
+#undef STACK
+#define STACK 9
+#include "dino_resource.asl"
+
+#undef STACK
+#define STACK A
+#include "dino_resource.asl"
+
+#undef STACK
+#define STACK B
+#include "dino_resource.asl"
+
+/* ***** Uncore Stacks **** */
+#undef STACK
+#define STACK D
+#include "ubox_resource.asl"
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pch.asl b/src/soc/intel/xeon_sp/spr/acpi/pch.asl
new file mode 100644
index 0000000000..05b7d58c50
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/pch.asl
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+OperationRegion (TMEM, PCI_Config, 0x00, 0x0100)
+Field (TMEM, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x40),
+	    ,   4,
+	BSEG,   4,
+	PAMS,   48,
+	Offset (0x52),
+	DIM0,   4,
+	DIM1,   4,
+	Offset (0x54),
+	DIM2,   4
+}
+
+Name (MTBL, Package (0x10)
+{
+	0x00,
+	0x20,
+	0x20,
+	0x30,
+	0x40,
+	0x40,
+	0x60,
+	0x80,
+	0x80,
+	0x80,
+	0x80,
+	0xC0,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0200
+})
+Name (ERNG, Package (0x0D)
+{
+	0x000C0000,
+	0x000C4000,
+	0x000C8000,
+	0x000CC000,
+	0x000D0000,
+	0x000D4000,
+	0x000D8000,
+	0x000DC000,
+	0x000E0000,
+	0x000E4000,
+	0x000E8000,
+	0x000EC000,
+	0x000F0000
+})
+Name (PAMB, Buffer (0x07){})
+
+Device (APIC)
+{
+	Name (_HID, EisaId ("PNP0003") /* IO-APIC Interrupt Controller */)
+	Name (_CRS, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadOnly, 0xFEC00000, 0x00100000)
+	})
+}
+
+Device (LPCB)
+{
+	Name (_ADR, 0x001F0000)
+	Name (_DDN, "LPC Bus Device")
+
+	Device (DMAC)
+	{
+		Name (_HID, EisaId ("PNP0200") /* PC-class DMA Controller */)
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+				0x0000,             // Range Minimum
+				0x0000,             // Range Maximum
+				0x00,               // Alignment
+				0x10,               // Length
+				)
+			IO (Decode16,
+				0x0081,             // Range Minimum
+				0x0081,             // Range Maximum
+				0x00,               // Alignment
+				0x03,               // Length
+				)
+			IO (Decode16,
+				0x0087,             // Range Minimum
+				0x0087,             // Range Maximum
+				0x00,               // Alignment
+				0x01,               // Length
+				)
+			IO (Decode16,
+				0x0089,             // Range Minimum
+				0x0089,             // Range Maximum
+				0x00,               // Alignment
+				0x03,               // Length
+				)
+			IO (Decode16,
+				0x008F,             // Range Minimum
+				0x008F,             // Range Maximum
+				0x00,               // Alignment
+				0x01,               // Length
+				)
+			IO (Decode16,
+				0x00C0,             // Range Minimum
+				0x00C0,             // Range Maximum
+				0x00,               // Alignment
+				0x20,               // Length
+				)
+			DMA (Compatibility, NotBusMaster, Transfer8, )
+				{4}
+		})
+	}
+
+	Device (RTC)
+	{
+		Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */)
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+				0x0070,             // Range Minimum
+				0x0070,             // Range Maximum
+				0x01,               // Alignment
+				0x02,               // Length
+				)
+			IO (Decode16,
+				0x0072,             // Range Minimum
+				0x0072,             // Range Maximum
+				0x01,               // Alignment
+				0x02,               // Length
+				)
+			IO (Decode16,
+				0x0074,             // Range Minimum
+				0x0074,             // Range Maximum
+				0x01,               // Alignment
+				0x04,               // Length
+				)
+			IRQNoFlags ()
+				{8}
+		})
+	}
+
+	Device (PIC)
+	{
+		Name (_HID, EisaId ("PNP0000") /* 8259-compatible Programmable Interrupt Controller */)
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+				0x0020,             // Range Minimum
+				0x0020,             // Range Maximum
+				0x01,               // Alignment
+				0x1E,               // Length
+				)
+			IO (Decode16,
+				0x00A0,             // Range Minimum
+				0x00A0,             // Range Maximum
+				0x01,               // Alignment
+				0x1E,               // Length
+				)
+			IO (Decode16,
+				0x04D0,             // Range Minimum
+				0x04D0,             // Range Maximum
+				0x01,               // Alignment
+				0x02,               // Length
+				)
+		})
+	}
+
+	Device (FPU)
+	{
+		Name (_HID, EisaId ("PNP0C04") /* x87-compatible Floating Point Processing Unit */)
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+				0x00F0,             // Range Minimum
+				0x00F0,             // Range Maximum
+				0x01,               // Alignment
+				0x01,               // Length
+				)
+			IRQNoFlags ()
+				{13}
+		})
+	}
+
+	Device (TMR)
+	{
+		Name (_HID, EisaId ("PNP0100"))
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+				0x0040,             // Range Minimum
+				0x0040,             // Range Maximum
+				0x01,               // Alignment
+				0x04,               // Length
+				)
+			IO (Decode16,
+				0x0050,             // Range Minimum
+				0x0050,             // Range Maximum
+				0x01,               // Alignment
+				0x04,               // Length
+				)
+			IRQNoFlags ()
+				{0}
+		})
+	}
+
+	Device (SPKR)
+	{
+		Name (_HID, EisaId ("PNP0800"))
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+				0x0061,             // Range Minimum
+				0x0061,             // Range Maximum
+				0x01,               // Alignment
+				0x01,               // Length
+				)
+		})
+	}
+
+	Device (XTRA)
+	{
+		Name (_HID, EisaId ("PNP0C02"))
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16,
+				0x0500,             // Range Minimum
+				0x0500,             // Range Maximum
+				0x01,               // Alignment
+				0xFF,               // Length
+				)
+			IO (Decode16,
+				0x0400,             // Range Minimum
+				0x0400,             // Range Maximum
+				0x01,               // Alignment
+				0x20,               // Length
+				)
+			IO (Decode16,
+				0x0010,             // Range Minimum
+				0x0010,             // Range Maximum
+				0x01,               // Alignment
+				0x10,               // Length
+				)
+			IO (Decode16,
+				0x0080,             // Range Minimum
+				0x0080,             // Range Maximum
+				0x01,               // Alignment
+				0x01,               // Length
+				)
+			IO (Decode16,
+				0x0084,             // Range Minimum
+				0x0084,             // Range Maximum
+				0x01,               // Alignment
+				0x03,               // Length
+				)
+			IO (Decode16,
+				0x0088,             // Range Minimum
+				0x0088,             // Range Maximum
+				0x01,               // Alignment
+				0x01,               // Length
+				)
+			IO (Decode16,
+				0x008C,             // Range Minimum
+				0x008C,             // Range Maximum
+				0x01,               // Alignment
+				0x03,               // Length
+				)
+			IO (Decode16,
+				0x0090,             // Range Minimum
+				0x0090,             // Range Maximum
+				0x01,               // Alignment
+				0x10,               // Length
+				)
+			IO (Decode16,
+				0x0600,             // Range Minimum
+				0x0600,             // Range Maximum
+				0x01,               // Alignment
+				0x20,               // Length
+				)
+			IO (Decode16,
+				0x0CA0,             // Range Minimum
+				0x0CA0,             // Range Maximum
+				0x01,               // Alignment
+				0x02,               // Length
+				)
+			IO (Decode16,
+				0x0CA4,             // Range Minimum
+				0x0CA4,             // Range Maximum
+				0x01,               // Alignment
+				0x03,               // Length
+				)
+			Memory32Fixed (ReadOnly,
+				0xFF000000,         // Address Base
+				0x01000000,         // Address Length
+				)
+		})
+	}
+
+	Device (HPET)
+	{
+		Name (_HID, EisaId ("PNP0103") /* HPET System Timer */)
+		Method (_STA, 0, NotSerialized)  // _STA: Status
+		{
+			Return (0x0F)
+		}
+
+		Name (CRS0, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite,
+			0xFED00000,         // Address Base
+			0x00000400,         // Address Length
+			)
+		})
+		Name (CRS1, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite,
+			0xFED01000,         // Address Base
+			0x00000400,         // Address Length
+			)
+		})
+		Name (CRS2, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite,
+			0xFED02000,         // Address Base
+			0x00000400,         // Address Length
+			)
+		})
+		Name (CRS3, ResourceTemplate ()
+		{
+			Memory32Fixed (ReadWrite,
+			0xFED03000,         // Address Base
+			0x00000400,         // Address Length
+			)
+		})
+		Method (_CRS, 0, Serialized)
+		{
+			Return (CRS0) /* \_SB_.PC00.HPET.CRS0 */
+		}
+    }
+}
+
+Device (HDAS)
+{
+	Name (_ADR, 0x001F0003)
+	OperationRegion (HDAR, PCI_Config, 0x00, 0x0100)
+	Field (HDAR, WordAcc, NoLock, Preserve)
+	{
+		VDID,   32
+	}
+
+	Name (_S0W, 0x03)  // _S0W: S0 Device Wake State
+	Method (_DSW, 3, NotSerialized)  // _DSW: Device Sleep Wake
+	{
+	}
+}
+
+Scope (\_GPE)
+{
+	OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0xFF)
+	Field (PMIO, ByteAcc, NoLock, Preserve) {
+		Offset(0x34),   /* 0x34, SMI/SCI STS*/
+			,  9,
+		SGCS, 1,        /* SWGPE STS BIT */
+
+		Offset(0x40),   /* 0x40, SMI/SCI_EN*/
+			,  17,
+		SGPC, 1,        /* SWGPE CTRL BIT */
+
+		Offset(0x6C),   /* 0x6C, General Purpose Event 0 Status [127:96] */
+			,  2,
+		SGPS,  1,       /* SWGPE STATUS */
+
+		Offset(0x7C),   /* 0x7C, General Purpose Event 0 Enable [127:96] */
+			,  2,
+		SGPE,  1        /* SWGPE ENABLE */
+	}
+	Device (RAS)
+	{
+		Name (_HID, EisaId ("PNP0C33"))
+		Name (_UID, 0)
+		Name (_DDN, "RAS Error Device Controller")
+		Printf ("Initialized RAS Device PNP0C33")
+	}
+	Method(_L62, 0) {
+		Printf ("SWGPE Method _L62")
+		SGPC = 0 // clear SWGPE enable
+		SGPS = 1 // clear SWGPE Status
+		Notify(RAS, 0x80)
+	}
+
+}
+
+#include "pch_rp.asl"
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pch_rp.asl b/src/soc/intel/xeon_sp/spr/acpi/pch_rp.asl
new file mode 100644
index 0000000000..c3a910406f
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/pch_rp.asl
@@ -0,0 +1,705 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+Device (RP01)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x00080000)
+	}
+
+	Name (SLOT, 0x01)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP02)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x00090000)
+	}
+
+	Name (SLOT, 0x02)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP03)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x000A0000)
+	}
+
+	Name (SLOT, 0x03)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP04)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x000B0000)
+	}
+
+	Name (SLOT, 0x04)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP05)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x000C0000)
+	}
+
+	Name (SLOT, 0x05)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP06)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x000D0000)
+	}
+
+	Name (SLOT, 0x06)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP07)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x000E0000)
+	}
+
+	Name (SLOT, 0x07)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP08)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x000F0000)
+	}
+
+	Name (SLOT, 0x08)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP09)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x00100000)
+	}
+
+	Name (SLOT, 0x09)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP10)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x00110000)
+	}
+
+	Name (SLOT, 0x0A)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP11)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x00120000)
+	}
+
+	Name (SLOT, 0x0B)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP12)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x00130000)
+	}
+
+	Name (SLOT, 0x0C)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP13)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x001A0000)
+	}
+
+	Name (SLOT, 0x0D)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP14)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x001B0000)
+	}
+
+	Name (SLOT, 0x0E)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP15)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x001C0000)
+	}
+
+	Name (SLOT, 0x0F)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
+
+Device (RP16)
+{
+	Name (LTRZ, 0x00)
+	Name (LMSL, 0x00)
+	Name (LNSL, 0x00)
+	Method (_ADR, 0, NotSerialized)
+	{
+		Return (0x001C0000)
+	}
+
+	Name (SLOT, 0x10)
+
+	OperationRegion (PXCS, PCI_Config, 0x00, 0x0900)
+	Field (PXCS, AnyAcc, NoLock, Preserve)
+	{
+		VDID,   32,
+		Offset (0x60),
+		Offset (0x62),
+		PSPX,   1
+	}
+
+	Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0xCC),
+		Offset (0xCE),
+		PMSX,   1
+	}
+
+	Method (HPME, 0, Serialized)
+	{
+		If (VDID != 0xFFFFFFFF && PMSX == 0x01)
+		{
+			Notify (PXSX, 0x02) // Device Wake
+			PMSX = 0x01
+			PSPX = 0x01
+		}
+	}
+
+	Device (PXSX)
+	{
+		Name (_ADR, 0x00)
+	}
+}
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
new file mode 100644
index 0000000000..7988a16242
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define _IIO_DEVICE_NAME(str, skt, stk)     str##skt##stk
+#define IIO_DEVICE_NAME(str, skt, stk)      _IIO_DEVICE_NAME(str, skt, stk)
+#define IIO_RESOURCE_NAME(res, str, skt, stk)      res##str##skt##stk
+
+#define STR(s)  #s
+#define _IIO_DEVICE_UID(str, skt, stk)      STR(str##skt##stk)
+#define IIO_DEVICE_UID(str, skt, stk)       _IIO_DEVICE_UID(str, skt, stk)
+
+Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK))
+{
+	Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)
+	Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)
+	Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK))
+	External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK))
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK))
+	}
+	Method (_PRT, 0, NotSerialized)
+	{
+		Return (\_SB.PRTID)
+	}
+	External (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
+	Method (_CRS, 0, NotSerialized)
+	{
+		Return (\_SB.IIO_DEVICE_NAME(RESPREFIX, SOCKET, STACK))
+	}
+	Name (SUPP, 0x00)
+	Name (CTRL, 0x00)
+	Name (_PXM, SOCKET)  /* _PXM: Device Proximity */
+	Method (_OSC, 4, NotSerialized)
+	{
+		CreateDWordField (Arg3, 0x00, CDW1)
+		If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)
+		{
+			CreateDWordField (Arg3, 0x04, CDW2)
+			If (Arg2 > 0x02)
+			{
+				CreateDWordField (Arg3, 0x08, CDW3)
+			}
+			SUPP = CDW2
+			CTRL = CDW3
+			If (SUPP & 0x16 != 0x16)
+			{
+				CTRL &= 0x1E
+				Sleep (0x03E8)
+			}
+			/* Never allow SHPC (no SHPC controller in system) */
+			CTRL &= 0x1D
+			/* Disable Native PCIe AER handling from OS */
+			CTRL &= 0x17
+
+			If (Arg1 != 1) /* unknown revision */
+			{
+				CDW1 |= 0x08
+			}
+			If (CDW3 != CTRL) /* capabilities bits were masked */
+			{
+				CDW1 |= 0x10
+			}
+			CDW3 = CTRL
+			Return (Arg3)
+		}
+		Else
+		{
+			/* indicate unrecognized UUID */
+			CDW1 |= 0x04
+			IO80 = 0xEE
+			Return (Arg3)
+		}
+	}
+}
diff --git a/src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
new file mode 100644
index 0000000000..416150fdf4
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#undef PRTID
+#define PRTID AR10
+
+#undef DEVPREFIX
+#define DEVPREFIX  UC
+#undef RESPREFIX
+#define RESPREFIX  UT
+#include "pci_resource.asl"
+
+#undef PRTID
+#define PRTID AR11
+
+#undef DEVPREFIX
+#define DEVPREFIX  UD
+#undef RESPREFIX
+#define RESPREFIX  UU
+#include "pci_resource.asl"
diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
new file mode 100644
index 0000000000..c1b8bdca35
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+Scope (\_SB)
+{
+	#include "uncore_irq.asl"
+
+	#define SOCKET 0
+	#include "iiostack.asl"
+	#undef SOCKET
+
+	#if CONFIG(SOC_ACPI_HEST)
+		Method (_OSC, 4, NotSerialized)
+		{
+			CreateDWordField (Arg3, 0x00, CDW1)
+			CDW1 |= 0x10 /* enable apei */
+			Return (Arg3)
+		}
+	#endif
+
+	#if (CONFIG_MAX_SOCKET > 1)
+		#define SOCKET 1
+		#include "iiostack.asl"
+		#undef SOCKET
+	#endif
+
+	#if (CONFIG_MAX_SOCKET > 2)
+		#define SOCKET 2
+		#include "iiostack.asl"
+		#undef SOCKET
+	#endif
+
+	#if (CONFIG_MAX_SOCKET > 3)
+		#define SOCKET 3
+		#include "iiostack.asl"
+		#undef SOCKET
+	#endif
+}
diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl
new file mode 100644
index 0000000000..699be7ee8f
--- /dev/null
+++ b/src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl
@@ -0,0 +1,381 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* IRQ mode has not been tested. */
+
+Name (AR00, Package() {
+	// D31
+	Package(){0x001FFFFF, 0, 0, 16 },
+	Package(){0x001FFFFF, 1, 0, 17 },
+	Package(){0x001FFFFF, 2, 0, 18 },
+	Package(){0x001FFFFF, 3, 0, 19 },
+	// D30
+	Package(){0x001EFFFF, 0, 0, 16 },
+	Package(){0x001EFFFF, 1, 0, 17 },
+	Package(){0x001EFFFF, 2, 0, 18 },
+	Package(){0x001EFFFF, 3, 0, 19 },
+	// D29
+	Package(){0x001DFFFF, 0, 0, 16 },
+	Package(){0x001DFFFF, 1, 0, 17 },
+	Package(){0x001DFFFF, 2, 0, 18 },
+	Package(){0x001DFFFF, 3, 0, 19 },
+	// D28
+	Package(){0x001CFFFF, 0, 0, 16 },
+	Package(){0x001CFFFF, 1, 0, 17 },
+	Package(){0x001CFFFF, 2, 0, 18 },
+	Package(){0x001CFFFF, 3, 0, 19 },
+	// D27
+	Package(){0x001BFFFF, 0, 0, 16 },
+	Package(){0x001BFFFF, 1, 0, 17 },
+	Package(){0x001BFFFF, 2, 0, 18 },
+	Package(){0x001BFFFF, 3, 0, 19 },
+	// D26
+	Package(){0x001AFFFF, 0, 0, 16 },
+	Package(){0x001AFFFF, 1, 0, 17 },
+	Package(){0x001AFFFF, 2, 0, 18 },
+	Package(){0x001AFFFF, 3, 0, 19 },
+	// D25
+	Package(){0x0019FFFF, 0, 0, 16 },
+	Package(){0x0019FFFF, 1, 0, 17 },
+	Package(){0x0019FFFF, 2, 0, 18 },
+	Package(){0x0019FFFF, 3, 0, 19 },
+	// D24
+	Package(){0x0018FFFF, 0, 0, 16 },
+	Package(){0x0018FFFF, 1, 0, 17 },
+	Package(){0x0018FFFF, 2, 0, 18 },
+	Package(){0x0018FFFF, 3, 0, 19 },
+	// D23
+	Package(){0x0017FFFF, 0, 0, 16 },
+	Package(){0x0017FFFF, 1, 0, 17 },
+	Package(){0x0017FFFF, 2, 0, 18 },
+	Package(){0x0017FFFF, 3, 0, 19 },
+	// D22
+	Package(){0x0016FFFF, 0, 0, 16 },
+	Package(){0x0016FFFF, 1, 0, 17 },
+	Package(){0x0016FFFF, 2, 0, 18 },
+	Package(){0x0016FFFF, 3, 0, 19 },
+	// D21
+	Package(){0x0015FFFF, 0, 0, 16 },
+	Package(){0x0015FFFF, 1, 0, 17 },
+	Package(){0x0015FFFF, 2, 0, 18 },
+	Package(){0x0015FFFF, 3, 0, 19 },
+	// D20
+	Package(){0x0014FFFF, 0, 0, 16 },
+	Package(){0x0014FFFF, 1, 0, 17 },
+	Package(){0x0014FFFF, 2, 0, 18 },
+	Package(){0x0014FFFF, 3, 0, 19 },
+	// D19
+	Package(){0x0013FFFF, 0, 0, 16 },
+	Package(){0x0013FFFF, 1, 0, 17 },
+	Package(){0x0013FFFF, 2, 0, 18 },
+	Package(){0x0013FFFF, 3, 0, 19 },
+	// D18
+	Package(){0x0012FFFF, 0, 0, 16 },
+	Package(){0x0012FFFF, 1, 0, 17 },
+	Package(){0x0012FFFF, 2, 0, 18 },
+	Package(){0x0012FFFF, 3, 0, 19 },
+	// D17
+	Package(){0x0011FFFF, 0, 0, 16 },
+	Package(){0x0011FFFF, 1, 0, 17 },
+	Package(){0x0011FFFF, 2, 0, 18 },
+	Package(){0x0011FFFF, 3, 0, 19 },
+	// D16
+	Package(){0x0010FFFF, 0, 0, 16 },
+	Package(){0x0010FFFF, 1, 0, 17 },
+	Package(){0x0010FFFF, 2, 0, 18 },
+	Package(){0x0010FFFF, 3, 0, 19 },
+	// D15
+	Package(){0x000FFFFF, 0, 0, 16 },
+	Package(){0x000FFFFF, 1, 0, 17 },
+	Package(){0x000FFFFF, 2, 0, 18 },
+	Package(){0x000FFFFF, 3, 0, 19 },
+	// D14
+	Package(){0x000EFFFF, 0, 0, 16 },
+	Package(){0x000EFFFF, 1, 0, 17 },
+	Package(){0x000EFFFF, 2, 0, 18 },
+	Package(){0x000EFFFF, 3, 0, 19 },
+	// D13
+	Package(){0x000DFFFF, 0, 0, 16 },
+	Package(){0x000DFFFF, 1, 0, 17 },
+	Package(){0x000DFFFF, 2, 0, 18 },
+	Package(){0x000DFFFF, 3, 0, 19 },
+	// D12
+	Package(){0x000CFFFF, 0, 0, 16 },
+	Package(){0x000CFFFF, 1, 0, 17 },
+	Package(){0x000CFFFF, 2, 0, 18 },
+	Package(){0x000CFFFF, 3, 0, 19 },
+	// D11
+	Package(){0x000BFFFF, 0, 0, 16 },
+	Package(){0x000BFFFF, 1, 0, 17 },
+	Package(){0x000BFFFF, 2, 0, 18 },
+	Package(){0x000BFFFF, 3, 0, 19 },
+	// D10
+	Package(){0x000AFFFF, 0, 0, 16 },
+	Package(){0x000AFFFF, 1, 0, 17 },
+	Package(){0x000AFFFF, 2, 0, 18 },
+	Package(){0x000AFFFF, 3, 0, 19 },
+	// D9
+	Package(){0x0009FFFF, 0, 0, 16 },
+	Package(){0x0009FFFF, 1, 0, 17 },
+	Package(){0x0009FFFF, 2, 0, 18 },
+	Package(){0x0009FFFF, 3, 0, 19 },
+	// D8
+	Package(){0x0008FFFF, 0, 0, 16 },
+	Package(){0x0008FFFF, 1, 0, 17 },
+	Package(){0x0008FFFF, 2, 0, 18 },
+	Package(){0x0008FFFF, 3, 0, 19 },
+
+	// [IIM0]: IIOMISC on PC00
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+	// [RLK0]: Legacy PCI Express Port 0 on PC00
+	Package() { 0x0003FFFF, 0, 0, 16 },
+	Package() { 0x0007FFFF, 0, 0, 16 },
+})
+
+Name (AR01, Package() {
+	// [IIM0]: IIOMISC on PCxx(non PC00)
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+	// [BRPA]: PCI Express Port A
+	Package() { 0x0001FFFF, 0, 0, 16 },
+	Package() { 0x0001FFFF, 1, 0, 17 },
+	Package() { 0x0001FFFF, 2, 0, 18 },
+	Package() { 0x0001FFFF, 3, 0, 19 },
+	// [BRPB]: PCI Express Port B
+	Package() { 0x0002FFFF, 0, 0, 16 },
+	Package() { 0x0002FFFF, 1, 0, 17 },
+	Package() { 0x0002FFFF, 2, 0, 18 },
+	Package() { 0x0002FFFF, 3, 0, 19 },
+	// [BRPC]: PCI Express Port C
+	Package() { 0x0003FFFF, 0, 0, 16 },
+	Package() { 0x0003FFFF, 1, 0, 17 },
+	Package() { 0x0003FFFF, 2, 0, 18 },
+	Package() { 0x0003FFFF, 3, 0, 19 },
+	// [BRPD]: PCI Express Port D
+	Package() { 0x0004FFFF, 0, 0, 16 },
+	Package() { 0x0004FFFF, 1, 0, 17 },
+	Package() { 0x0004FFFF, 2, 0, 18 },
+	Package() { 0x0004FFFF, 3, 0, 19 },
+	// [BRPE]: PCI Express Port E
+	Package() { 0x0005FFFF, 0, 0, 16 },
+	Package() { 0x0005FFFF, 1, 0, 17 },
+	Package() { 0x0005FFFF, 2, 0, 18 },
+	Package() { 0x0005FFFF, 3, 0, 19 },
+	// [BRPF]: PCI Express Port F
+	Package() { 0x0006FFFF, 0, 0, 16 },
+	Package() { 0x0006FFFF, 1, 0, 17 },
+	Package() { 0x0006FFFF, 2, 0, 18 },
+	Package() { 0x0006FFFF, 3, 0, 19 },
+	// [BRPG]: PCI Express Port G
+	Package() { 0x0007FFFF, 0, 0, 16 },
+	Package() { 0x0007FFFF, 1, 0, 17 },
+	Package() { 0x0007FFFF, 2, 0, 18 },
+	Package() { 0x0007FFFF, 3, 0, 19 },
+	// [BRPH]: PCI Express Port H
+	Package() { 0x0008FFFF, 0, 0, 16 },
+	Package() { 0x0008FFFF, 1, 0, 17 },
+	Package() { 0x0008FFFF, 2, 0, 18 },
+	Package() { 0x0008FFFF, 3, 0, 19 },
+	// [NTBR]: NTB IRQ routing table
+	Package() { 0x0009FFFF, 0, 0, 16 },
+	Package() { 0x0009FFFF, 1, 0, 17 },
+	Package() { 0x0009FFFF, 2, 0, 18 },
+	Package() { 0x0009FFFF, 3, 0, 19 },
+	// D23: SATA Port 0
+	Package() { 0x0017FFFF, 0, 0, 16 },
+	Package() { 0x0017FFFF, 1, 0, 17 },
+	Package() { 0x0017FFFF, 2, 0, 18 },
+	Package() { 0x0017FFFF, 3, 0, 19 },
+	// D24: SATA Port 1
+	Package() { 0x0018FFFF, 0, 0, 16 },
+	Package() { 0x0018FFFF, 1, 0, 17 },
+	Package() { 0x0018FFFF, 2, 0, 18 },
+	Package() { 0x0018FFFF, 3, 0, 19 },
+	// D25: SATA Port 2
+	Package() { 0x0019FFFF, 0, 0, 16 },
+	Package() { 0x0019FFFF, 1, 0, 17 },
+	Package() { 0x0019FFFF, 2, 0, 18 },
+	Package() { 0x0019FFFF, 3, 0, 19 },
+	// D31: PCH devices
+	Package() { 0x001FFFFF, 0, 0, 16 },
+	Package() { 0x001FFFFF, 1, 0, 17 },
+	Package() { 0x001FFFFF, 2, 0, 18 },
+	Package() { 0x001FFFFF, 3, 0, 19 },
+})
+
+Name (AR02, Package() {
+	// [BRPA]: PCI Express Port A
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR03, Package() {
+	// [BRPB]: PCI Express Port B
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR04, Package() {
+	// [BRPC]: PCI Express Port C
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR05, Package() {
+	// [BRPD]: PCI Express Port D
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR06, Package() {
+	// [BRPE]: PCI Express Port E
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR07, Package() {
+	// [BRPF]: PCI Express Port F
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR08, Package() {
+	// [BRPG]: PCI Express Port G
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR09, Package() {
+	// [BRPH]: PCI Express Port H
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})
+
+Name (AR0A, Package() {
+	// [NTBR]: NTB IRQ routing table
+	Package() { 0x0009FFFF, 0, 0, 16 },
+	Package() { 0x0009FFFF, 1, 0, 17 },
+	Package() { 0x0009FFFF, 2, 0, 18 },
+	Package() { 0x0009FFFF, 3, 0, 19 },
+})
+
+Name (AR10, Package() {
+	// [UBX0]: Uncore 0 UBOX Device
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+	// [CSM0]: Uncore 0 CHASIS_SMBUS Devices
+	Package() { 0x000BFFFF, 0, 0, 16 },
+	Package() { 0x000BFFFF, 1, 0, 17 },
+	Package() { 0x000BFFFF, 2, 0, 18 },
+	Package() { 0x000BFFFF, 3, 0, 19 },
+	// [M2M0]: Uncore 0 MS2MEM_SCF_MS2MEM0 Device
+	Package() { 0x000CFFFF, 0, 0, 16 },
+	Package() { 0x000CFFFF, 1, 0, 17 },
+	Package() { 0x000CFFFF, 2, 0, 18 },
+	Package() { 0x000CFFFF, 3, 0, 19 },
+	// [M2M1]: Uncore 0 MS2MEM_SCF_MS2MEM1 Device
+	Package() { 0x000DFFFF, 0, 0, 16 },
+	Package() { 0x000DFFFF, 1, 0, 17 },
+	Package() { 0x000DFFFF, 2, 0, 18 },
+	Package() { 0x000DFFFF, 3, 0, 19 },
+	// [MCD0]: Uncore 0 MCDDR0 Device
+	Package() { 0x001AFFFF, 0, 0, 16 },
+	Package() { 0x001AFFFF, 1, 0, 17 },
+	Package() { 0x001AFFFF, 2, 0, 18 },
+	Package() { 0x001AFFFF, 3, 0, 19 },
+	// [MCD1]: Uncore 0 MCDDR1 Device
+	Package() { 0x001BFFFF, 0, 0, 16 },
+	Package() { 0x001BFFFF, 1, 0, 17 },
+	Package() { 0x001BFFFF, 2, 0, 18 },
+	Package() { 0x001BFFFF, 3, 0, 19 },
+})
+
+Name (AR11, Package() {
+	// [CHA1]: Uncore 1 GRP1_CHA8-10 Device
+	Package() { 0x0001FFFF, 0, 0, 16 },
+	Package() { 0x0001FFFF, 1, 0, 17 },
+	Package() { 0x0001FFFF, 2, 0, 18 },
+	Package() { 0x0001FFFF, 3, 0, 19 },
+	// [CHA2]: Uncore 1 GRP0_CHA0-7 Device
+	Package() { 0x000AFFFF, 0, 0, 16 },
+	Package() { 0x000AFFFF, 1, 0, 17 },
+	Package() { 0x000AFFFF, 2, 0, 18 },
+	Package() { 0x000AFFFF, 3, 0, 19 },
+	// [CHA3]: Uncore 1 GRP0_CHA8-10 Device
+	Package() { 0x00B0FFFF, 0, 0, 16 },
+	Package() { 0x00B0FFFF, 1, 0, 17 },
+	Package() { 0x00B0FFFF, 2, 0, 18 },
+	Package() { 0x00B0FFFF, 3, 0, 19 },
+	// [CA00]: Uncore 1 CHAALL0-1 Device
+	Package() { 0x001DFFFF, 0, 0, 16 },
+	Package() { 0x001DFFFF, 1, 0, 17 },
+	Package() { 0x001DFFFF, 2, 0, 18 },
+	Package() { 0x001DFFFF, 3, 0, 19 },
+	// [PUC0]: Uncore 1 CHASIS_PUINT0-7 Device
+	Package() { 0x001EFFFF, 0, 0, 16 },
+	Package() { 0x001EFFFF, 1, 0, 17 },
+	Package() { 0x001EFFFF, 2, 0, 18 },
+	Package() { 0x001EFFFF, 3, 0, 19 },
+	// [GN30]: Uncore 1 Gen3Phy Device
+	Package() { 0x001FFFFF, 0, 0, 16 },
+	Package() { 0x001FFFFF, 1, 0, 17 },
+	Package() { 0x001FFFFF, 2, 0, 18 },
+	Package() { 0x001FFFFF, 3, 0, 19 },
+})
+
+Name (AR12, Package() {
+	// [IIO]: MISC Device
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+	// [IIO]: DSA0 Device
+	Package() { 0x0001FFFF, 0, 0, 16 },
+	Package() { 0x0001FFFF, 1, 0, 17 },
+	Package() { 0x0001FFFF, 2, 0, 18 },
+	Package() { 0x0001FFFF, 3, 0, 19 },
+	// [IIO]: IAX0 Device
+	Package() { 0x0002FFFF, 0, 0, 16 },
+	Package() { 0x0002FFFF, 1, 0, 17 },
+	Package() { 0x0002FFFF, 2, 0, 18 },
+	Package() { 0x0002FFFF, 3, 0, 19 },
+	// [IIO]: MSM Device
+	Package() { 0x0003FFFF, 0, 0, 16 },
+	Package() { 0x0003FFFF, 1, 0, 17 },
+	Package() { 0x0003FFFF, 2, 0, 18 },
+	Package() { 0x0003FFFF, 3, 0, 19 },
+	// [IIO]: NPK0 Device
+	Package() { 0x0004FFFF, 0, 0, 16 },
+	Package() { 0x0004FFFF, 1, 0, 17 },
+	Package() { 0x0004FFFF, 2, 0, 18 },
+	Package() { 0x0004FFFF, 3, 0, 19 },
+})
+
+Name (AR13, Package() {
+	//  PCH PCIE express port IRQ routing table, which need align with the definition from AR00
+	Package() { 0x0000FFFF, 0, 0, 16 },
+	Package() { 0x0000FFFF, 1, 0, 17 },
+	Package() { 0x0000FFFF, 2, 0, 18 },
+	Package() { 0x0000FFFF, 3, 0, 19 },
+})