diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2024-02-18 11:45:30 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2024-03-05 21:26:39 +0000 |
| commit | 0201d989f20b3157d52fb9dca01256ebe6550126 (patch) | |
| tree | b7747a88f5aa0706037b49716247d8ef4896bb63 /src/soc/intel/xeon_sp/spr/Kconfig | |
| parent | 67166a7eb231dcb3cff5c5b8b407cebcfe6f753f (diff) | |
drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the FSP heap is right above the
RC heap, where both of them are located at the bottom part of CAR.
Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/spr/Kconfig')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index bb88becaa7..ace5c07042 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -13,6 +13,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP select SOC_INTEL_CSE_SERVER_SKU select XEON_SP_COMMON_BASE select HAVE_IOAT_DOMAINS + select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND help Intel Sapphire Rapids-SP support |