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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-15 16:42:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:32:21 +0000 |
| commit | bf46ba5adbd7cec13986d8b6584a2a14bfc9109e (patch) | |
| tree | d9bfc58519625a71f03f14858b56c814ec22dde0 /src/soc/intel/xeon_sp/smihandler.c | |
| parent | 9abeb9c0626244e5f889536bbc9de0bf685eb922 (diff) | |
soc/intel/xeon_sp: correct wrong gpio register base offsets
Reference: Intel doc# 633935-005 and 547817 rev1.5.
Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/smihandler.c')
0 files changed, 0 insertions, 0 deletions