soc/intel/xeon_sp: Read IOAPIC ID from hardware

Currently coreboot hardcodes the same IOAPIC IDs as used on UEFI native,
however FSP does not program the IOAPIC IDs, except for PCH IOAPIC.

Drop existing code that hardcodes PCI addresses and IOAPIC IDs and
detect the IOAPIC inside the domain automatically, read the IOAPIC
base address and let existing code figure out the IOAPIC ID by reading
it back from HW.

Change-Id: I2543a46dcc4a98ec8629530ca87882a7106c9ed1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84850
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

2 files changed, 2 insertions, 23 deletions

diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index e245bfb5dd..78393c1330 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -186,8 +186,8 @@
 #define VMD_DEV_NUM             0x05
 #define VMD_FUNC_NUM            0x05
 
-#define APIC_DEV_NUM            0x05
-#define APIC_FUNC_NUM           0x00
+// Per stack PCI IOAPIC (BxD5F4)
+#define APIC_ABAR		0x40
 
 // DMI3 B0D0F0 registers
 #define DMI3_DEVID		0x2020
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index ed6fa4c544..387b5668f5 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -119,27 +119,6 @@ void config_reset_cpl3_csrs(void)
 }
 #endif
 
-uint8_t soc_get_iio_ioapicid(int socket, int stack)
-{
-	uint8_t ioapic_id = socket ? 0xf : 0x9;
-	switch (stack) {
-	case CSTACK:
-		break;
-	case PSTACK0:
-		ioapic_id += 1;
-		break;
-	case PSTACK1:
-		ioapic_id += 2;
-		break;
-	case PSTACK2:
-		ioapic_id += 3;
-		break;
-	default:
-		return 0xff;
-	}
-	return ioapic_id;
-}
-
 bool is_memtype_reserved(uint16_t mem_type)
 {
 	return !!(mem_type & MEM_TYPE_RESERVED);