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authorJonathan Zhang <jonzhang@meta.com>2023-01-23 18:14:53 -0800
committerFelix Held <felix-coreboot@felixheld.de>2023-03-09 21:39:17 +0000
commitca520a726a6d47c31c5a8c278e2a272b1f89bac4 (patch)
treee58fdcdce41799990df27fa4d83ccabe1a3f58a2 /src/soc/intel/xeon_sp/skx
parent2285b72d0684f958ab372948d17f2da89db456c7 (diff)
soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specifics
Intel SPR-SP has its specific way to get the bus number of ubox. Move the current implementations to CPX-SP and SKX-SP folders. Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/skx')
-rw-r--r--src/soc/intel/xeon_sp/skx/include/soc/soc_util.h2
-rw-r--r--src/soc/intel/xeon_sp/skx/soc_util.c19
2 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
index 526f5a6a3c..8c81f431d7 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
@@ -10,7 +10,9 @@ void config_reset_cpl3_csrs(void);
const struct SystemMemoryMapHob *get_system_memory_map(void);
+uint8_t get_stack_busno(const uint8_t stack);
uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
+uint32_t get_socket_ubox_busno(uint32_t socket);
int soc_get_stack_for_port(int port);
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 628613829a..b501a3e04f 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -60,6 +60,17 @@ bool is_iio_stack_res(const STACK_RES *res)
return res->BusBase < res->BusLimit;
}
+uint8_t get_stack_busno(const uint8_t stack)
+{
+ if (stack >= MAX_IIO_STACK) {
+ printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
+ return 0;
+ }
+ const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
+ const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
+ return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
+}
+
uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
{
const IIO_UDS *hob = get_iio_uds();
@@ -69,6 +80,14 @@ uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
}
+uint32_t get_socket_ubox_busno(uint32_t socket)
+{
+ if (socket == 0)
+ return get_stack_busno(PCU_IIO_STACK);
+
+ return get_socket_stack_busno(socket, PCU_IIO_STACK);
+}
+
void config_reset_cpl3_csrs(void)
{
uint32_t data, plat_info, max_min_turbo_limit_ratio;