diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-04-01 14:47:52 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-16 06:56:13 +0000 |
| commit | 4fad28f4c199bd783fcdfe1b09298f26a28159da (patch) | |
| tree | 6822a2a4358d17cd08c452dbfa9b245e6ee3331d /src/soc/intel/xeon_sp/skx/include | |
| parent | 352ca5b0313c514b438c4aa518be905a6eff001f (diff) | |
soc/intel/xeon_sp: More PCU locks
Add the following locks as recommended by the Intel docs:
DRAM_POWER_INFO_LOCK
PCU_CR3_FLEX_RATIO_LOCK
TURBO_ACTIVATION_RATIO_LOCK
PCU_CR0_PMAX_LOCK
Change-Id: I8d8211977e87109a91790a4070454fc561aa761b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/skx/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index c7af810b91..96239baf03 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -26,11 +26,18 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define SAD_ALL_PAM456_CSR 0x44 +#if !defined(__SIMPLE_DEVICE__) +#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#else +#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#endif + #define PCU_IIO_STACK 1 #define PCU_DEV 30 #define PCU_CR1_FUN 1 #define PCU_CR0_FUN 0 +#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_P_STATE_LIMITS 0xd8 #define P_STATE_LIMITS_LOCK_SHIFT 31 @@ -40,6 +47,8 @@ #define PCU_CR0_CURRENT_CONFIG 0xf8 #define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ #define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) +#define PCU_CR0_PMAX 0xf0 +#define PMAX_LOCK BIT(31) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c |