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| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-28 13:25:06 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-29 10:49:03 +0000 |
| commit | b544fe48af76e5aae7537d95b62191e1fed2bc45 (patch) | |
| tree | 1a4ec089b065138d084dcedbf0d4f0f3e4eed752 /src/soc/intel/xeon_sp/nb_acpi.c | |
| parent | 68e597d81e41bb2d93558e4a4da26f0892f34d86 (diff) | |
mb/intel/adlrvp: Add dq_pins_interleaved into 'struct mb_cfg'
List of changes:
1. Split mem_cfg for DDR4 and LPDDR4 as per board_id
2. Move dq_pins_interleaved into board-specific memory configuration
information
TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs.
Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46873
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/nb_acpi.c')
0 files changed, 0 insertions, 0 deletions