soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 22 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
new file mode 100644
index 0000000000..79ab47eaed
--- /dev/null
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <cpu/x86/smm.h>
+#include <soc/pci_devs.h>
+
+void smm_region(uintptr_t *start, size_t *size)
+{
+	uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR);
+	uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR);
+
+	tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB);
+	tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB);
+	/* Only the upper [31:20] bits of an address are checked against
+	 * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this
+	 * effectively means +1MiB for the limit.
+	 */
+	tseg_limit += 1 * MiB;
+
+	*start = tseg_base;
+	*size = tseg_limit - tseg_base;
+}