diff options
author | Jonathan Zhang <jonzhang@fb.com> | 2020-01-16 11:16:45 -0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-06 08:19:59 +0000 |
commit | 8f89549d3c7d41643337662947cfdb2329bd030b (patch) | |
tree | 81d337d1e0bc655d82f47ba8808f42713942dc6a /src/soc/intel/xeon_sp/lpc.c | |
parent | e425a09d6a0016e128373941ee1cf223a528a0fc (diff) |
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable
Processor, which is a processor in Xeon-SP family. The code
is expected to be reusable for future geneations of Xeon-SP
processors, and will be updated with smaller targeted
patches accordingly, to add support for additional Xeon-SP
processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a
proof-of-concept build. The binary is not shared in public,
when this patch is upstreamed.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/lpc.c')
-rw-r--r-- | src/soc/intel/xeon_sp/lpc.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c new file mode 100644 index 0000000000..b0ba68147b --- /dev/null +++ b/src/soc/intel/xeon_sp/lpc.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/ioapic.h> +#include <intelblocks/lpc_lib.h> +#include <soc/soc_util.h> +#include <soc/iomap.h> + +static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { + { 0, 0 } +}; + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) +{ + return xeon_lpc_fixed_mmio_ranges; +} + +void lpc_soc_init(struct device *dev) +{ + printk(BIOS_SPEW, "pch: lpc_init\n"); + + /* FSP configures IOAPIC and PCHInterrupt Config */ + printk(BIOS_SPEW, "IOAPICID 0x%x, 0x%x\n", + io_apic_read((void *)IO_APIC_ADDR, 0x00), + ((io_apic_read((void *)IO_APIC_ADDR, 0x00) & 0x0f000000) >> 24)); +} + +void pch_lpc_soc_fill_io_resources(struct device *dev) +{ +} |