diff options
| author | Jingle Hsu <jingle_hsu@wiwynn.com> | 2020-07-01 18:26:49 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-12 19:36:42 +0000 |
| commit | e07ea4cd38c5c232515a8755d2b4fbff6f12b949 (patch) | |
| tree | 9cda898ea1131ddb757366fd65d8c75904e505d3 /src/soc/intel/xeon_sp/include | |
| parent | 145a76182c58e2b83b2081d2545b5fa190e6930c (diff) | |
soc/intel/xeon_sp: Add RTC failure checking
Add a weak function mainboard_rtc_failed() for mainboard customization.
Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper
triggered event.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pmc.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/romstage.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index d3bad1b715..49e58d366a 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -25,6 +25,6 @@ #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) - +#define RTC_BATTERY_DEAD (1 << 2) #endif diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 42425e29d0..8bd5709fe0 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -8,5 +8,6 @@ /* These functions are weak and can be overridden by a mainboard functions. */ void mainboard_memory_init_params(FSPM_UPD * mupd); +void mainboard_rtc_failed(void); #endif /* _SOC_ROMSTAGE_H_ */ |