diff options
| author | Gang Chen <gang.c.chen@intel.com> | 2024-05-18 07:46:00 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-07-03 12:09:06 +0000 |
| commit | cae81a567462b4ab2494b4e6cee0ee20ea4a2fcf (patch) | |
| tree | 2fb8fe52e1975c9e12c2858556673cf9ee0ecdf8 /src/soc/intel/xeon_sp/include | |
| parent | 409860687baf68ac3f4f27d234f6e08afa6ad309 (diff) | |
soc/intel/xeon_sp/gnr: Support fast boot
Fast boot will used pre-saved hardware configuration data to
accelerate the boot process, e.g. DDR training is skipped by using
pre-saved training data. Enable fast boot on cold and warm resets
by default.
Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/config.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/config.h b/src/soc/intel/xeon_sp/include/soc/config.h index 6d5f3d587d..66538f5a28 100644 --- a/src/soc/intel/xeon_sp/include/soc/config.h +++ b/src/soc/intel/xeon_sp/include/soc/config.h @@ -11,4 +11,12 @@ enum xeonsp_cxl_mode { enum xeonsp_cxl_mode get_cxl_mode(void); +enum xeonsp_fast_boot_mode { + XEONSP_FAST_BOOT_DISABLED = 0x0, + XEONSP_FAST_BOOT_COLD = 0x1, + XEONSP_FAST_BOOT_WARM = 0x2, +}; + +enum xeonsp_fast_boot_mode get_fast_boot_mode(void); + #endif |