diff options
| author | Rocky Phagura <rphagura@fb.com> | 2020-05-23 20:29:00 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-02 07:37:08 +0000 |
| commit | c62c98a884231ef36bf3eb613b2d24e37c89c4d2 (patch) | |
| tree | 031e3f0a1cd9f4d5c7b578b08174a9001ef18710 /src/soc/intel/xeon_sp/include | |
| parent | a895344936594402175b2f4321b0e1a9d5dbfe7b (diff) | |
soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and
to check SMI status registers. The architecture of Lewisburg PCH is very
similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.
TEST=build for Tiogapass and check ACPI base. Log message will now show
pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing
to io port 0x500.
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/bootblock.h | 11 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pch.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pmc.h | 32 |
3 files changed, 44 insertions, 11 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h new file mode 100644 index 0000000000..6be4370454 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_XEON_SP_BOOTBLOCK_H_ +#define _SOC_XEON_SP_BOOTBLOCK_H_ + +#include "iomap.h" + +/* Bootblock post console init programming */ +void bootblock_pch_init(void); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h new file mode 100644 index 0000000000..84d5e4896b --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PCH_H_ +#define _SOC_PCH_H_ + +#include <device/device.h> + +#if ENV_RAMSTAGE +void pch_disable_devfn(struct device *dev); +#endif + +#endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 74343f84c8..d3bad1b715 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -3,18 +3,28 @@ #ifndef _SOC_PMC_H_ #define _SOC_PMC_H_ -/* PCI Configuration Space (D31:F2): PMC */ -#define PMC_ACPI_CNT 0x44 + /* PCI Configuration Space (D31:F2): PMC */ +#define ABASE 0x40 +#define ACTL 0x44 +#define PMC_ACPI_CNT 0x44 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) +#define SCI_IRQ_ADJUST 0 -#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define PWRMBASE 0x48 +#define GEN_PMCON_A 0xa0 +#define SMI_LOCK (1 << 4) +#define GEN_PMCON_B 0xa4 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) -#define SCI_IRQ_ADJUST 0 #endif |