diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-23 13:40:28 -0800 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2023-01-29 06:38:19 +0000 |
| commit | 7a7cdf8efbd93f3fa935b0386ad5529c8d6d4960 (patch) | |
| tree | 377dbb5c196f9fc9c5f09f9fa4a2385e7407cc40 /src/soc/intel/xeon_sp/include | |
| parent | 5edb51855c2c8885bb1ea4fc3780728b6acd516e (diff) | |
soc/intel/xeon_sp/include/soc/pmc.h: move to lbg directory
The PMC registers are quite different between LBG and EBG. Move pmc.h
to lbg directory to differentiate.
Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pmc.h | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h deleted file mode 100644 index d49986339c..0000000000 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_PMC_H_ -#define _SOC_PMC_H_ - - /* PCI Configuration Space (D31:F2): PMC */ -#define ABASE 0x40 -#define ACTL 0x44 -#define PMC_ACPI_CNT 0x44 -#define PWRM_EN (1 << 8) -#define ACPI_EN (1 << 7) -#define SCI_IRQ_SEL (7 << 0) -#define SCI_IRQ_ADJUST 0 - -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 -#define PWRMBASE 0x48 -#define GEN_PMCON_A 0xa0 -#define DISB (1 << 23) -#define MS4V (1 << 18) -#define GBL_RST_STS (1 << 16) -#define SMI_LOCK (1 << 4) -#define GEN_PMCON_B 0xa4 -#define SLP_STR_POL_LOCK (1 << 18) -#define ACPI_BASE_LOCK (1 << 17) -#define RTC_BATTERY_DEAD (1 << 2) -#define SUS_PWR_FLR (1 << 14) -#define HOST_RST_STS (1 << 9) -#define PWR_FLR (1 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) - -/* Memory mapped IO registers in PMC */ -#define PMSYNC_TPR_CFG 0xc8 -#define PMSYNC_LOCK (1 << 15) -#define PCH_PWRM_ACPI_TMR_CTL 0xfc -#define ACPI_TIM_DIS (1 << 1) -#define GPIO_GPE_CFG 0x120 -#define GPE0_DWX_MASK 0xf -#define GPE0_DW_SHIFT(x) (4 * (x)) -#define GBLRST_CAUSE0 0x124 -#define GBLRST_CAUSE1 0x128 -#endif |