diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-24 23:57:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-03 09:33:47 +0000 |
| commit | 6b93866f5ef5efae6542011ad1c84afc86f1bda1 (patch) | |
| tree | 32fe7bbe0048f4cdf9eff3973c318e42b49cddc6 /src/soc/intel/xeon_sp/include | |
| parent | f6f1258673d4c2382e3014904563380c13f4eeec (diff) | |
soc/intel/xeon_sp: disable PM ACPI timer if chosen
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is
disabled. This is done to bring SKL, CNL, DNV in line with the other
platforms, in order to transition handling of the PM timer from FSP to
coreboot in the follow-up changes.
Disabling is done in `finalize` since FSP makes use of the PMtimer.
Without PM Timer emulation disabling it too early would block.
Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pmc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index bbdb60bb4b..69299b6057 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -36,6 +36,8 @@ /* Memory mapped IO registers in PMC */ #define PMSYNC_TPR_CFG 0xc8 #define PMSYNC_LOCK (1 << 15) +#define PCH_PWRM_ACPI_TMR_CTL 0xfc +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4 * (x)) |