diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-04-06 14:09:30 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-18 20:32:24 +0000 |
| commit | 64c6223759870286f9f344e0cd8663f582b3e0f1 (patch) | |
| tree | 4efc9222a64c43772b9f5ffdd7425adb0b7a4ec2 /src/soc/intel/xeon_sp/include | |
| parent | df40ca9d41ab1fcab3ddea3ce3c9aa95ab0da2b0 (diff) | |
soc/intel/xeon_sp: Set MSR locks
Set MSR locks as indicated by the Intel documents.
The following MSRs settings are locked:
MSR_FEATURE_CONFIG AES enable/disable lock
TURBO_ACTIVATION_RATIO_LOCK
This also adds PARALLEL_MP_AP_WORK to enable running on APs to set
each CPU MSR.
Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/msr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index dd05adc83f..3d68bf2565 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -5,6 +5,9 @@ #include <intelblocks/msr.h> +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_LOCK BIT(0) + #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff #define IA32_MCG_CAP_CTL_P_BIT 8 |