diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2020-12-02 11:33:02 -0700 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-22 02:59:18 +0000 |
| commit | 63e2a84d598276608f2cd48dc87824c959a328f5 (patch) | |
| tree | 3e0cd7bc6de1453f0db84b27bbab76057695424e /src/soc/intel/xeon_sp/include | |
| parent | f65945fe8c2ae3d225d23aa27f8784d1d37027ac (diff) | |
soc/intel/xeon_sp: Use common block ACPI
Use the common block ACPI to further reduce the duplicate code.
Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/acpi.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pm.h | 6 |
2 files changed, 6 insertions, 12 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 743251b5fc..a236843920 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -11,20 +11,8 @@ typedef struct { uint8_t buf[32]; } MEM_BLK; -/* P-state configuration */ -#define PSS_MAX_ENTRIES 16 -#define PSS_RATIO_STEP 1 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 - unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -uint32_t soc_read_sci_irq_select(void); -int soc_madt_sci_irq_polarity(int sci); -void soc_power_states_generation(int core, int cores_per_package); -acpi_tstate_t *soc_get_tss_table(int *entries); -acpi_cstate_t *soc_get_cstate_map(size_t *entries); -int calculate_power(int tdp, int p1_ratio, int ratio); void uncore_inject_dsdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index f5a45c6106..5087e4f68b 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -70,6 +70,12 @@ #define ENABLE_SMI_PARAMS \ (APMC_EN | GBL_SMI_EN | EOS) +/* P-state configuration */ +#define PSS_MAX_ENTRIES 16 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + /* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ #define ETR 0xac #define CF9_LOCK (1 << 31) |