diff options
| author | Jincheng Li <jincheng.li@intel.com> | 2024-03-13 15:06:26 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-26 10:10:48 +0000 |
| commit | 31998020458af821cb61d0000ee2cbd0293958f6 (patch) | |
| tree | 280829f2d75b7c2582f4d5ad5308e7fdebbcd635 /src/soc/intel/xeon_sp/include | |
| parent | e17113a3f3f3d6ccf5f79bea7c405e983860bc52 (diff) | |
soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms
DDR support codes across generations are similar. Share the codes
to improve code reuse.
TEST=intel/archercity CRB
Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/ddr.h | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/ddr.h b/src/soc/intel/xeon_sp/include/soc/ddr.h new file mode 100644 index 0000000000..bb10caaf1f --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/ddr.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_DDR_H_ +#define _SOC_DDR_H_ + +#include <types.h> + +/* SPD Byte 11: Module Nominal Voltage + * currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */ +#define SPD_VDD_DDR4 3 +#define SPD_VDD_DDR5 0 +#define SPD_TYPE_DDR5 0x12 + +/* DDR_*_TCK_MIN are in picoseconds */ +#define DDR_800_TCK_MIN 2500 +#define DDR_1000_TCK_MIN 2000 +#define DDR_1066_TCK_MIN 1875 +#define DDR_1200_TCK_MIN 1667 +#define DDR_1333_TCK_MIN 1500 +#define DDR_1400_TCK_MIN 1429 +#define DDR_1600_TCK_MIN 1250 +#define DDR_1800_TCK_MIN 1110 +#define DDR_1866_TCK_MIN 1071 +#define DDR_2000_TCK_MIN 1000 +#define DDR_2133_TCK_MIN 938 +#define DDR_2200_TCK_MIN 909 +#define DDR_2400_TCK_MIN 833 +#define DDR_2600_TCK_MIN 769 +#define DDR_2666_TCK_MIN 750 +#define DDR_2800_TCK_MIN 714 +#define DDR_2933_TCK_MIN 682 +#define DDR_3000_TCK_MIN 667 +#define DDR_3200_TCK_MIN 625 +#define DDR_3400_TCK_MIN 589 +#define DDR_3466_TCK_MIN 577 +#define DDR_3600_TCK_MIN 556 +#define DDR_3733_TCK_MIN 536 +#define DDR_3800_TCK_MIN 527 +#define DDR_4000_TCK_MIN 500 +#define DDR_4200_TCK_MIN 477 +#define DDR_4266_TCK_MIN 469 +#define DDR_4400_TCK_MIN 455 +#define DDR_4800_TCK_MIN 417 +#define DDR_5200_TCK_MIN 385 +#define DDR_5600_TCK_MIN 358 +#define DDR_6000_TCK_MIN 334 +#define DDR_6400_TCK_MIN 313 +#define DDR_6800_TCK_MIN 295 +#define DDR_7200_TCK_MIN 278 +#define DDR_7600_TCK_MIN 264 +#define DDR_8000_TCK_MIN 250 +#define DDR_8400_TCK_MIN 239 + +unsigned int get_max_memory_speed(unsigned int commonTck); +unsigned int get_ddr_millivolt(unsigned int ddr_voltage); +uint32_t get_ddr_voltage(uint8_t DdrVoltage); + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t slot); + +#endif /* _SOC_DDR_H_ */ |