diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2020-12-08 21:55:32 -0700 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2020-12-10 17:33:34 +0000 |
| commit | c0bdf89ff458f84e332aa861809a23997ce1b905 (patch) | |
| tree | e43e1d635989247c20d79e576b7c4fcfed02a217 /src/soc/intel/xeon_sp/include | |
| parent | 4def30d550a58ff7fa599c41cddb7ffca7e5077e (diff) | |
soc/intel/xeon_sp/nvs: Use common global NVS
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there
isn't anything uncommon with the soc NVS, use the Intel common NVS.
This covers the NVS cases of common code used by xeon_sp. Update
the mainboards for this change.
Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/nvs.h | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h index 100a442178..512945898e 100644 --- a/src/soc/intel/xeon_sp/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -3,18 +3,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include <stdint.h> +#include <intelblocks/nvs.h> -/* TODO - this requires xeon sp, server board support */ -/* NOTE: We do not use intelblocks/nvs.h since it includes - mostly client specific attributes */ - -/* TODO: This is not aligned with the ACPI asl code */ -struct __packed global_nvs { - uint8_t pcnt; /* 0x00 - Processor Count */ - uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t uior; - uint8_t rsvd3[250]; -}; - -#endif /* _SOC_NVS_H_ */ +#endif |