From c0bdf89ff458f84e332aa861809a23997ce1b905 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 8 Dec 2020 21:55:32 -0700 Subject: soc/intel/xeon_sp/nvs: Use common global NVS The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there isn't anything uncommon with the soc NVS, use the Intel common NVS. This covers the NVS cases of common code used by xeon_sp. Update the mainboards for this change. Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Jay Talbott --- src/soc/intel/xeon_sp/include/soc/nvs.h | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) (limited to 'src/soc/intel/xeon_sp/include') diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h index 100a442178..512945898e 100644 --- a/src/soc/intel/xeon_sp/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -3,18 +3,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include +#include -/* TODO - this requires xeon sp, server board support */ -/* NOTE: We do not use intelblocks/nvs.h since it includes - mostly client specific attributes */ - -/* TODO: This is not aligned with the ACPI asl code */ -struct __packed global_nvs { - uint8_t pcnt; /* 0x00 - Processor Count */ - uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t uior; - uint8_t rsvd3[250]; -}; - -#endif /* _SOC_NVS_H_ */ +#endif -- cgit v1.2.3