soc/xeon_sp: Initially add N-1 IBL codes

N-1 IBL (Integrated Boot Logic) codes are initially forked from
EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL
codes are a set of stub codes to fulfill build sanity check for GNR
SoC and CRB codes before the formal codes are published.

Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/ibl/Makefile.mk b/src/soc/intel/xeon_sp/ibl/Makefile.mk
new file mode 100644
index 0000000000..a92d559827
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ibl/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += soc_gpio.c soc_pch.c
+romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
+ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ibl/include