soc/intel/xeon_sp/gnr: Support full IIO UPD configurations

Change-Id: Iebfadffd2da83992af983b8c0dfe2706f81eb728
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84317
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 62 insertions, 28 deletions

diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/iio.h b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h
index cbc9113792..16095d1f3e 100644
--- a/src/soc/intel/xeon_sp/gnr/include/soc/iio.h
+++ b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h
@@ -44,31 +44,39 @@ struct iio_port_config {
 	uint8_t	vpp_mux_address;		// SMBUS address of MUX used to access VPP
 	uint8_t	vpp_mux_channel;		// Channel of the MUX used to access VPP
 
-	uint8_t	slot_eip:1;			// Electromechanical Interlock Present -
+	uint8_t	npem_address;			// SMBUS address of IO expander which provides NPEM
+	uint8_t	npem_bank;			// Port or bank on IoExpander which provides NPEM
+	uint8_t	npem_mux_address;		// SMBUS address of MUX used to access NPEM
+	uint8_t	npem_mux_channel;		// Channel of the MUX used to access NPEM
+
+	uint8_t	slot_eip;			// Electromechanical Interlock Present -
 						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
-	uint8_t	slot_hps:1;			// Hot Plug surprise supported -
+	uint8_t	slot_hps;			// Hot Plug surprise supported -
 						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
-	uint8_t	slot_pind:1;			// Power Indicator Present -
+	uint8_t	slot_pind;			// Power Indicator Present -
 						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
-	uint8_t	slot_aind:1;			// Attention Inductor Present -
+	uint8_t	slot_aind;			// Attention Inductor Present -
 						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
-	uint8_t	slot_pctl:1;			// Power Controller Present -
+	uint8_t	slot_pctl;			// Power Controller Present -
 						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
-	uint8_t	slot_abtn:1;			// Attention Button Present -
+	uint8_t	slot_abtn;			// Attention Button Present -
 						//   Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
-	uint8_t	slot_rsvd:2;			// Reserved
 
-	uint8_t	vpp_enabled:1;			// If VPP is supported on given port
-	uint8_t	vpp_exp_type:1;			// IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE
+	uint8_t	vpp_enabled;			// If VPP is supported on given port
+	uint8_t	vpp_exp_type;			// IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE
 						//   for values definitions)
+	uint8_t	npem_supported;			// If NPEM is supported on given port
 
-	uint8_t	slot_implemented:1;
-	uint8_t	reserved:4;
+	uint8_t	slot_implemented;
+	uint8_t	retimer_1_present;
+	uint8_t	retimer_2_present;
+	uint8_t	common_clock;
+	uint8_t	sris;
 
-	uint16_t hot_plug:1;			// If hotplug is supported on slot connected to this port
-	uint16_t mrl_sensor_present:1;		// If MRL is present on slot connected to this port
-	uint16_t slot_power_limit_scale:2;	// Slot Power Scale for slot connected to this port
-	uint16_t slot_power_limit_value:12;	// Slot Power Value for slot connected to this port
+	uint16_t hot_plug;			// If hotplug is supported on slot connected to this port
+	uint16_t mrl_sensor_present;		// If MRL is present on slot connected to this port
+	uint16_t slot_power_limit_scale;	// Slot Power Scale for slot connected to this port
+	uint16_t slot_power_limit_value;	// Slot Power Value for slot connected to this port
 
 	uint16_t physical_slot_number;		// Slot number for slot connected to this port
 };
@@ -77,8 +85,8 @@ struct iio_pe_config {
 	uint8_t			socket;
 	IIO_PACKAGE_PE		pe;
 	IIO_BIFURCATION		bifurcation;
-	uint8_t			cxl_support:1;
-	uint8_t			reserved:7;
+	uint8_t			cxl_support;
+	uint8_t			reserved;
 	struct iio_port_config	port_config[MAX_IIO_PORTS_PER_STACK];
 };
 
@@ -102,11 +110,12 @@ struct iio_pe_config {
 	.reserved		= 0,\
 	.port_config		=
 
-/* TODO: to update rsv1 - rsv5 after SoC launch */
 #define _IIO_PORT_CFG_STRUCT(vppen, vppex, vaddr, vport, vmuxa, vmuxc,\
-		slteip, slthps, sltpind, sltaind, sltpctl, sltabtn, hotp, mrlsp,\
-		sltimpl, sltpls, sltplv, psn,\
-		rsv1, rsv2, rsv3, rsv4, rsv5) {\
+		slteip, slthps, sltpind, sltaind, sltpctl, sltabtn,\
+		sltimpl, hotp, mrlsp, sltpls, sltplv, psn,\
+		retimer1, retimer2, comclk, dsris,\
+		npmspt, npaddr, npb, npma, npmc\
+		) {\
 	.vpp_enabled		= (vppen),\
 	.vpp_exp_type		= (vppex),\
 	.vpp_address		= (vaddr),\
@@ -119,32 +128,57 @@ struct iio_pe_config {
 	.slot_aind		= (sltaind),\
 	.slot_pctl		= (sltpctl),\
 	.slot_abtn		= (sltabtn),\
-	.slot_rsvd		= 0,\
 	.slot_implemented	= (sltimpl),\
-	.reserved		= 0,\
+	.retimer_1_present	= (retimer1),\
+	.retimer_2_present	= (retimer2),\
+	.common_clock		= (comclk),\
+	.sris			= (dsris),\
 	.hot_plug		= (hotp),\
 	.mrl_sensor_present	= (mrlsp),\
 	.slot_power_limit_scale	= (sltpls),\
 	.slot_power_limit_value	= (sltplv),\
-	.physical_slot_number	= (psn)\
+	.physical_slot_number	= (psn),\
+	.npem_supported		= (npmspt),\
+	.npem_address		= (npaddr),\
+	.npem_bank		= (npb),\
+	.npem_mux_address	= (npma),\
+	.npem_mux_channel	= (npmc),\
 }
 
 #define _IIO_PORT_CFG_STRUCT_DISABLED \
-	_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
-		0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0)
+	_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+		0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+		0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+		0x0, 0x0, 0x0, 0x0,\
+		0x0, 0x0, 0x0, 0x0, 0x0)
 
 #define _IIO_PORT_CFG_STRUCT_X8 _IIO_PORT_CFG_STRUCT
 #define _IIO_PORT_CFG_STRUCT_X4 _IIO_PORT_CFG_STRUCT
 #define _IIO_PORT_CFG_STRUCT_X2 _IIO_PORT_CFG_STRUCT
 
 #define _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn)\
-	_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
-		0x0, 0x0, 0x0, 0x1, sltpls, sltplv, psn, 0x0, 0x0, 0x0, 0x0, 0x0)
+	_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+		0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
+		0x1, 0x0, 0x0, sltpls, sltplv, psn,\
+		0x0, 0x0, 0x1, 0x0,\
+		0x0, 0x0, 0x0, 0x0, 0x0)
 
 #define _IIO_PORT_CFG_STRUCT_BASIC_X8 _IIO_PORT_CFG_STRUCT_BASIC
 #define _IIO_PORT_CFG_STRUCT_BASIC_X4 _IIO_PORT_CFG_STRUCT_BASIC
 #define _IIO_PORT_CFG_STRUCT_BASIC_X2 _IIO_PORT_CFG_STRUCT_BASIC
 
+#define _IIO_PE_CFG_DISABLED(socket, pe) {\
+	_IIO_PE_CFG_STRUCT(socket, pe, IIO_BIFURCATE_AUTO, PE_TYPE_PCIE) {\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+		_IIO_PORT_CFG_STRUCT_DISABLED,\
+	}}
+
 void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_table,
 				unsigned int num_entries);