soc/intel/xeon_sp: Add Granite Rapids initial codes

coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.

This patch initially sets the code set up as a build target with
Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids).

1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmitsburg PCH)'s codes are reused.

2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.

Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

1 files changed, 21 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/gnr/chipset.cb b/src/soc/intel/xeon_sp/gnr/chipset.cb
new file mode 100644
index 0000000000..ef33eac9d2
--- /dev/null
+++ b/src/soc/intel/xeon_sp/gnr/chipset.cb
@@ -0,0 +1,21 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/gnr
+
+	# configure VT-d
+	register "vtd_support" = "1"
+
+	# configure BIOS lockdown
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_FSP,
+	}"
+
+	# configure devices
+	device cpu_cluster 0 on ops cpu_bus_ops end
+
+	device domain 0 on
+		device pci 00.0 mandatory end # MMAP/VT-d
+		device gpio 0 alias ibl_gpio_communities on end # GPIO
+		device mmio 0xfed00000 on ops hpet_device_ops end # HPET
+	end
+end