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authorPatrick Rudolph <patrick.rudolph@9elements.com>2024-03-21 08:05:03 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-03-23 18:05:34 +0000
commitcb92d28d7a22811f5399c589e5b231508ff42370 (patch)
tree6d2915cf77ddf5d1b2b11e040023e1f378a7954f /src/soc/intel/xeon_sp/ebg/Makefile.mk
parent2b24fc7c56da2fe23a3a94def166ff2872d058d5 (diff)
soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs. TEST=intel/archercity CRB Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/ebg/Makefile.mk')
-rw-r--r--src/soc/intel/xeon_sp/ebg/Makefile.mk2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/ebg/Makefile.mk b/src/soc/intel/xeon_sp/ebg/Makefile.mk
index ac73acbde9..b05c05bbb3 100644
--- a/src/soc/intel/xeon_sp/ebg/Makefile.mk
+++ b/src/soc/intel/xeon_sp/ebg/Makefile.mk
@@ -2,6 +2,6 @@
bootblock-y += soc_gpio.c soc_pch.c
romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
-ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
+ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include