diff options
| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-12-13 08:30:53 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-16 14:07:15 +0000 |
| commit | 3c31173c1c7c726438824e4e457042c14f815d21 (patch) | |
| tree | 4604b677360fd7eb3a9936c312d88788b7b9aa7f /src/soc/intel/xeon_sp/ebg/Makefile.inc | |
| parent | 5e9e7bff4b07cc23874ff07dd291ac09694baeca (diff) | |
soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset.
These changes are in accordance with the documentation:
* Intel(R) Emmitsburg Platform Controller Hub External Design
Specification. Document Number: 606161
* Emmitsburg PCH BIOS Specification. Document Number: 631063.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/ebg/Makefile.inc')
| -rw-r--r-- | src/soc/intel/xeon_sp/ebg/Makefile.inc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/ebg/Makefile.inc b/src/soc/intel/xeon_sp/ebg/Makefile.inc new file mode 100644 index 0000000000..ea29e2d853 --- /dev/null +++ b/src/soc/intel/xeon_sp/ebg/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += soc_gpio.c soc_pch.c +romstage-y += soc_gpio.c soc_pmutil.c +ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include |