summaryrefslogtreecommitdiff
path: root/src/soc/intel/xeon_sp/cpx
diff options
context:
space:
mode:
authorShuo Liu <shuo.liu@intel.com>2024-02-20 01:06:10 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-03-07 13:26:49 +0000
commita5bdf8e8df7c2afe0264c58537569d6142d145cd (patch)
treeaa933a0d633e7a9b7b43fd2ca71381b98034e6e9 /src/soc/intel/xeon_sp/cpx
parentcb6a35edd591fffa2e21a001a466d2fbd4baf04a (diff)
soc/intel/xeon_sp: Add memory type check utils
FSP memory type representations change across Xeon-SP SoCs. This patch adds type check utils to abstract the differences. TEST=intel/archercity CRB Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx')
-rw-r--r--src/soc/intel/xeon_sp/cpx/soc_util.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 5dbac98a2a..2d6005b08f 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -121,3 +121,18 @@ void get_iiostack_info(struct iiostack_resource *info)
}
}
}
+
+bool is_memtype_reserved(uint16_t mem_type)
+{
+ return !!(mem_type & MEM_TYPE_RESERVED);
+}
+
+bool is_memtype_non_volatile(uint16_t mem_type)
+{
+ return !(mem_type & MEMTYPE_VOLATILE_MASK);
+}
+
+bool is_memtype_processor_attached(uint16_t mem_type)
+{
+ return true;
+}