diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-10-27 15:11:05 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-04-14 10:50:44 +0000 |
| commit | 36e6f9bc047f86e1628c8c41d3ac16d80fb344de (patch) | |
| tree | 69c01a856551733abc0f2f324c52f842d7a2daf2 /src/soc/intel/xeon_sp/cpx | |
| parent | 4e498e169e698f3654d6163a28e19fbd5e31820a (diff) | |
soc/intel/xeon_sp: Don't sort struct device cpus for numa
Currently the xeon_sp code reassigns struct devices apic_id so that srat
entries can be added in a certain order.
This is not a good idea as it breaks thread local storage which contains
a pointer to its struct device cpu.
This moves the sorting of the lapic_ids to the srat table generation
and adds the numa node id in each core init entry. Now it is done in
parallel too as a bonus.
Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/cpu.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index f46d1a6f60..14535e2ee7 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -78,8 +78,9 @@ static void each_cpu_init(struct device *cpu) { msr_t msr; - printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, + cpu->path.apic.package_id); /* * Set HWP base feature, EPP reg enumeration, lock thermal and msr @@ -227,7 +228,4 @@ void mp_init_cpus(struct bus *bus) * rest of the CPU devices do not have chip_info updated. */ chip_config = bus->dev->chip_info; - - /* update numa domain for all cpu devices */ - xeonsp_init_cpu_config(); } |