diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2021-01-15 13:29:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-26 10:34:56 +0000 |
| commit | 31ed8856f9c6f06b8594f80b4abc39952ee84247 (patch) | |
| tree | 90404fbd39f6a6c452854d5b5b5c839bb487e677 /src/soc/intel/xeon_sp/cpx | |
| parent | 08de06ad6dc5530c23eced8363b15f5324ec41b1 (diff) | |
soc/intel/xeon_sp/acpi.c: Add ACPI C-State table
Add the soc ACPI _CST table.
The table may be customized to support the different state
combinations and set by the mainboard config.
Tested on deltalake with acpi_idle driver.
Note, intel_idle may not use ACPI _CST table.
Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 11 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 630bc8e979..1311678116 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <intelblocks/cfg.h> +#include <soc/acpi.h> #include <soc/gpio.h> #include <soc/irq.h> #include <stdint.h> @@ -96,6 +97,8 @@ struct soc_intel_xeon_sp_cpx_config { /* TCC activation offset */ uint32_t tcc_offset; + + enum acpi_cstate_mode cstate_states; }; typedef struct soc_intel_xeon_sp_cpx_config config_t; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 848cb48fbb..8f7f92a224 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -98,8 +98,19 @@ #define XHCI_BUS_NUMBER 0x0 #define PCH_DEV_SLOT_XHCI 0x14 #define XHCI_FUNC_NUM 0x0 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) + +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) + #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) |