soc/intel/xeon_sp: Enable SMI handler

SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.

TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.

NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.

Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 13 insertions, 5 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 28e7b83386..369d474552 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -78,6 +78,10 @@ config FSP_TEMP_RAM_SIZE
 	  documentation says this needs to be at least 128KiB, but practice
 	  show this needs to be 256KiB or more.
 
+config IED_REGION_SIZE
+	hex
+	default 0x400000
+
 config SOC_INTEL_COMMON_BLOCK_P2SB
 	def_bool y
 
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc
index b2e653e50e..a5c6848852 100644
--- a/src/soc/intel/xeon_sp/cpx/Makefile.inc
+++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc
@@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y)
 subdirs-y += ../../../../cpu/intel/turbo
 subdirs-y += ../../../../cpu/x86/lapic
 subdirs-y += ../../../../cpu/x86/mtrr
+subdirs-y += ../../../../cpu/x86/smm
 subdirs-y += ../../../../cpu/x86/tsc
 subdirs-y += ../../../../cpu/intel/microcode
 
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index d1bcbd7977..2f4ab0663e 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -7,7 +7,9 @@
 #include <console/debug.h>
 #include <cpu/cpu.h>
 #include <cpu/intel/common/common.h>
+#include <cpu/intel/em64t101_save_state.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
@@ -17,6 +19,7 @@
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/soc_util.h>
+#include <soc/smmrelocate.h>
 #include <soc/util.h>
 
 #include "chip.h"
@@ -172,16 +175,16 @@ static void post_mp_init(void)
 	/* Set Max Ratio */
 	set_max_turbo_freq();
 
-	/*
-	 * TODO: Now that all APs have been relocated as well as the BSP let SMIs
-	 * start flowing.
-	 */
-	if (0) global_smi_enable();
+	if (CONFIG(HAVE_SMI_HANDLER))
+		global_smi_enable();
 }
 
 static const struct mp_ops mp_ops = {
 	.pre_mp_init = pre_mp_init,
 	.get_cpu_count = get_thread_count,
+	.get_smm_info = get_smm_info,
+	.pre_mp_smm_init = smm_initialize,
+	.relocation_handler = smm_relocation_handler,
 	.get_microcode_info = get_microcode_info,
 	.post_mp_init = post_mp_init,
 };