diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-01-18 09:14:03 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-28 17:25:51 +0000 |
| commit | 106d7b30b93b9d5ad4826b7dc021be69458a554f (patch) | |
| tree | 01785042aab757a0f5fca525f1dba467982f0250 /src/soc/intel/xeon_sp/cpx | |
| parent | 3cfcffe49c720bd5152d3a26ec744adbc4f12477 (diff) | |
soc/intel/xeon_sp: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Intel Document-ID: 735086
Intel Document-ID: 612246
Tested: On SPR 4S all PCU on all 4 sockets could be found and locked.
Change-Id: I06694715cba76b101165f1cef66d161b0f896b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 56 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 4 |
2 files changed, 35 insertions, 25 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 1e84dd5a5c..6274f02f61 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -6,6 +6,7 @@ #include <cpu/x86/mp.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <intelblocks/lpc_lib.h> @@ -115,33 +116,38 @@ static void iio_enable_masks(void) static void set_pcu_locks(void) { - for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - - /* configure PCU_CR0_FUN csrs */ - const struct device *cr0_dev = PCU_DEV_CR0(bus); - pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); - pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); - pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); - - - /* configure PCU_CR1_FUN csrs */ - const struct device *cr1_dev = PCU_DEV_CR1(bus); - pci_or_config32(cr1_dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); - - /* configure PCU_CR2_FUN csrs */ - const struct device *cr2_dev = PCU_DEV_CR2(bus); - pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK); - pci_or_config32(cr2_dev, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR); - - /* configure PCU_CR3_FUN csrs */ - const struct device *cr3_dev = PCU_DEV_CR3(bus); - pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); - pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK); + struct device *dev = NULL; + + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR0_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); + pci_or_config32(dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, + PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(dev, PCU_CR0_TURBO_ACTIVATION_RATIO, + TURBO_ACTIVATION_RATIO_LOCK); } + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR1_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); + } + + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR2_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, + PP_PWR_LIM_LOCK); + pci_or_config32(dev, PCU_CR2_DRAM_POWER_INFO_UPR, + DRAM_POWER_INFO_LOCK_UPR); + } + + dev = NULL; + while ((dev = dev_find_device(PCI_VID_INTEL, PCU_CR3_DEVID, dev))) { + printk(BIOS_SPEW, "%s: locking registers\n", dev_path(dev)); + pci_or_config32(dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + pci_or_config32(dev, PCU_CR3_FLEX_RATIO, OC_LOCK); + } } static void set_imc_locks(void) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 587c97cd8b..614f42af08 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -24,6 +24,7 @@ #define PCU_DEV 30 #define PCU_CR0_FUN 0 +#define PCU_CR0_DEVID 0x344a #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 @@ -37,6 +38,7 @@ #define PMAX_LOCK BIT(31) #define PCU_CR1_FUN 1 +#define PCU_CR1_DEVID 0x344b #define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c @@ -64,6 +66,7 @@ #define SAPMCTL_LOCK_MASK BIT(31) #define PCU_CR2_FUN 2 +#define PCU_CR2_DEVID 0x344c #define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) @@ -72,6 +75,7 @@ #define PP_PWR_LIM_LOCK BIT(31) #define PCU_CR3_FUN 3 +#define PCU_CR3_DEVID 0x344d #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0x60 #define TDP_LOCK BIT(31) |