soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2

CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues
to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0.

Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE,
and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding
StackBase and StackSize FSP-M UPD parameters is removed.

Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable()
to indicate that FSP-S multi phase init is not enabled, since it is
not supported by CPX-SP FSP.

TESTED=booted YV3 config A to target OS.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c
new file mode 100644
index 0000000000..deb9030c20
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/ramstage.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+
+int soc_fsp_multi_phase_init_is_enable(void)
+{
+	return 0;
+}