From d4efb330c1d87ac9f16be4e97b70797dcbe4e3bc Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Wed, 22 Jul 2020 12:39:40 -0700 Subject: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2 CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0. Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed. Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP. TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049 Reviewed-by: Angel Pons Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/ramstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 src/soc/intel/xeon_sp/cpx/ramstage.c (limited to 'src/soc/intel/xeon_sp/cpx/ramstage.c') diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c new file mode 100644 index 0000000000..deb9030c20 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int soc_fsp_multi_phase_init_is_enable(void) +{ + return 0; +} -- cgit v1.2.3