diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-05-28 17:53:48 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-14 16:44:58 +0000 |
| commit | 3172f987fa632189ad3bb44d61614b58be0b142a (patch) | |
| tree | 93a586c8335b1cbafec9f9e5d823b7325476c8f1 /src/soc/intel/xeon_sp/cpx/include | |
| parent | 2c4866228e83e3dc4ae547356fe4be4ce4fda77b (diff) | |
soc/intel/xeon_sp/cpx: add NUMA ACPI tables
Add NUMA ACPI tables: SRAT, SLIT.
TESTED=Boot CPX-SP based server, check /sys/firmware/acpi/tables
for SRAT/SLIT tables.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I3374b802afd2d001e841afd85e7ae07bc27c01ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/acpi.h | 17 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h | 36 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h | 4 |
3 files changed, 57 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h new file mode 100644 index 0000000000..0f010ec85f --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ACPI_H_ +#define _SOC_ACPI_H_ + +#include <acpi/acpi.h> +#include <soc/nvs.h> + +#define MEM_BLK_COUNT 0x140 +typedef struct { + uint8_t buf[32]; +} MEM_BLK; + +unsigned long northbridge_write_acpi_tables(const struct device *device, + unsigned long current, struct acpi_rsdp *rsdp); + +#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 0e6f42ca63..4953f930f5 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -48,7 +48,43 @@ #define VTD_DEV 5 #define VTD_FUNC 0 +#define VMD_DEV_NUM 0x05 +#define VMD_FUNC_NUM 0x05 +#define APIC_DEV_NUM 0x05 +#define APIC_FUNC_NUM 0x04 + +#define CBDMA_DEV_NUM 0x04 +#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function + +#define PCH_IOAPIC_BUS_NUMBER 0x00 +#define PCH_IOAPIC_DEV_NUM 0x1F +#define PCH_IOAPIC_FUNC_NUM 0x00 + +/* PCH Device info */ + +#define XHCI_BUS_NUMBER 0x0 +#define PCH_DEV_SLOT_XHCI 0x14 +#define XHCI_FUNC_NUM 0x0 + +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0x00 + +// ==================== IOAPIC Definitions for DMAR/ACPI ==================== +#define PCH_IOAPIC_ID 0x08 +#define PC00_IOAPIC_ID 0x09 +#define PC01_IOAPIC_ID 0x0A +#define PC02_IOAPIC_ID 0x0B +#define PC03_IOAPIC_ID 0x0C +#define PC04_IOAPIC_ID 0x0D +#define PC05_IOAPIC_ID 0x0E +#define PC06_IOAPIC_ID 0x0F +#define PC07_IOAPIC_ID 0x10 +#define PC08_IOAPIC_ID 0x11 +#define PC09_IOAPIC_ID 0x12 +#define PC10_IOAPIC_ID 0x13 +#define PC11_IOAPIC_ID 0x14 #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 679ad4a3c0..1c3ca66c52 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -36,4 +36,8 @@ void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thre uint8_t *package, uint8_t *core, uint8_t *thread); unsigned int xeon_sp_get_cpu_count(void); +int get_platform_thread_count(void); +int get_threads_per_package(void); +const struct SystemMemoryMapHob *get_system_memory_map(void); + #endif /* _SOC_UTIL_H_ */ |