diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-03-11 07:14:07 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-30 13:38:18 +0000 |
| commit | ec58bebbd6dd6f4b7535948e55cd9241fac4378f (patch) | |
| tree | f39fa4bf43fdade7820a4ad15ba2c76f33109180 /src/soc/intel/xeon_sp/cpx/Makefile.mk | |
| parent | f7e456748f90bdf2798c09bfaa23b5e17de43d0d (diff) | |
soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
GraniteRapids (6th Gen Xeon-SP) FSP contains changes in IIO stack
descriptors impacting the way of coreboot's creation of domains.
Separates the codes as preparation for 6th Gen and later platforms.
Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.mk')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Makefile.mk | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index 095ad59af4..3eccfb0c61 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -10,6 +10,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c +ramstage-y += ../chip_gen1.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c |