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| author | Jingle Hsu <jingle_hsu@wiwynn.com> | 2020-08-11 20:48:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-18 08:48:04 +0000 |
| commit | a41b12cd7b8ffa1af1d7b0bc5eae799acd4f86da (patch) | |
| tree | 1429aceda89aff71f93458240d9b7dae0dce1fa8 /src/soc/intel/xeon_sp/cpx/Kconfig | |
| parent | 7749c34a11029c3cba6dbd280cd19852c57a304f (diff) | |
xeon_sp/cpx: Enable ACPI P-state support
Implement ACPI P-state support to enable driver acpi_cpufreq.
This patch leverages code from the Skylake project.
Tested=On OCP Delta Lake
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
1501000 1500000 1400000 1300000 1200000 1100000 1000000 900000 800000
Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Kconfig')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 0df9847d22..dcbadf8aab 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -72,6 +72,10 @@ config FSP_TEMP_RAM_SIZE config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y +config CPU_BCLK_MHZ + int + default 100 + select CACHE_MRC_SETTINGS # CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel |