From a41b12cd7b8ffa1af1d7b0bc5eae799acd4f86da Mon Sep 17 00:00:00 2001
From: Jingle Hsu <jingle_hsu@wiwynn.com>
Date: Tue, 11 Aug 2020 20:48:45 +0800
Subject: xeon_sp/cpx: Enable ACPI P-state support

Implement ACPI P-state support to enable driver acpi_cpufreq.
This patch leverages code from the Skylake project.

Tested=On OCP Delta Lake
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
1501000 1500000 1400000 1300000 1200000 1100000 1000000 900000 800000

Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/xeon_sp/cpx/Kconfig')

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 0df9847d22..dcbadf8aab 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -72,6 +72,10 @@ config FSP_TEMP_RAM_SIZE
 config SOC_INTEL_COMMON_BLOCK_P2SB
 	def_bool y
 
+config CPU_BCLK_MHZ
+	int
+	default 100
+
 select CACHE_MRC_SETTINGS
 
 # CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
-- 
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