soc/intel/xeon_sp: Add Granite Rapids initial codes

coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.

This patch initially sets the code set up as a build target with
Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids).

1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmitsburg PCH)'s codes are reused.

2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.

Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

1 files changed, 98 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c
new file mode 100644
index 0000000000..a1b1b6504f
--- /dev/null
+++ b/src/soc/intel/xeon_sp/chip_gen6.c
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpigen_pci.h>
+#include <assert.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <intelblocks/acpi.h>
+#include <post.h>
+#include <soc/acpi.h>
+#include <soc/chip_common.h>
+#include <soc/numa.h>
+#include <soc/soc_util.h>
+#include <soc/util.h>
+#include <stdlib.h>
+
+static const UDS_PCIROOT_RES *domain_to_pciroot_res(const struct device *dev)
+{
+	assert(dev->path.type == DEVICE_PATH_DOMAIN);
+	const union xeon_domain_path dn = {
+		.domain_path = dev->path.domain.domain
+	};
+
+	const IIO_UDS *hob = get_iio_uds();
+	assert(hob != NULL);
+
+	const UDS_STACK_RES *sr = &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack];
+	for (unsigned int index = 0; index < sr->PciRootBridgeNum; index++) {
+		if (sr->PciRoot[index].BusBase == dev->downstream->secondary)
+			return &sr->PciRoot[index];
+	}
+
+	return NULL;
+}
+
+static void iio_pci_domain_read_resources(struct device *dev)
+{
+	int index = 0;
+	struct resource *res;
+	const UDS_PCIROOT_RES *pr = domain_to_pciroot_res(dev);
+
+	/* Initialize the system-wide I/O space constraints. */
+	if (pr->IoBase <= pr->IoLimit) {
+		res = new_resource(dev, index++);
+		res->base = pr->IoBase;
+		res->limit = pr->IoLimit;
+		res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
+	}
+
+	/* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */
+	if (is_domain0(dev)) {
+		res = new_resource(dev, index++);
+		res->base = 0;
+		res->limit = 0xfff;
+		res->size = 0x1000;
+		res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	}
+
+	/* Initialize the system-wide memory resources constraints. */
+	if (pr->Mmio32Base <= pr->Mmio32Limit) {
+		res = new_resource(dev, index++);
+		res->base = pr->Mmio32Base;
+		res->limit = pr->Mmio32Limit;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+	}
+
+	/* Initialize the system-wide memory resources constraints. */
+	if (pr->Mmio64Base <= pr->Mmio64Limit) {
+		res = new_resource(dev, index++);
+		res->base = pr->Mmio64Base;
+		res->limit = pr->Mmio64Limit;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+	}
+}
+
+static struct device_operations iio_pcie_domain_ops = {
+	.read_resources = iio_pci_domain_read_resources,
+	.set_resources = pci_domain_set_resources,
+	.scan_bus = pci_host_bridge_scan_bus,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_name = soc_acpi_name,
+	.write_acpi_tables = northbridge_write_acpi_tables,
+	.acpi_fill_ssdt	= pci_domain_fill_ssdt,
+#endif
+};
+
+void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus,
+				const xSTACK_RES *sr, const size_t pci_segment_group)
+{
+	for (unsigned int index = 0; index < sr->PciRootBridgeNum; index++) {
+		const UDS_PCIROOT_RES *pr = &sr->PciRoot[index];
+		create_domain(dp, bus,
+			pr->BusBase,
+			pr->BusLimit,
+			pciroot_res_to_domain_type(sr, pr),
+			&iio_pcie_domain_ops,
+			pci_segment_group);
+	}
+}