diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-06-19 06:48:45 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-06-28 11:27:41 +0000 |
| commit | 2eb9d5ed62d3c3a4484c686af12d29a390ccf963 (patch) | |
| tree | 103455b274fda0d467be62b3401fcb27c9a9445f /src/soc/intel/xeon_sp/chip_gen1.c | |
| parent | 0a6f5188e80d888529e2067d02add19f65cb013c (diff) | |
soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
For Gen1 SoCs, the range starting from the end of VTd BAR to the end
of 32-bit domain MMIO resource window is reserved for unknown devices.
Get them reserved.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/xeon_sp/chip_gen1.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/chip_gen1.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index 117de9ca00..a68c764662 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <intelblocks/acpi.h> +#include <intelblocks/vtd.h> #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/soc_util.h> @@ -54,6 +55,13 @@ static void iio_pci_domain_read_resources(struct device *dev) if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) domain_mem_window_from_to(dev, index++, sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1); + + /* Declare domain reserved MMIO */ + uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(pcidev_on_root(0, 0)); + if ((reserved_mmio >= sr->PciResourceMem32Base) && + (reserved_mmio <= sr->PciResourceMem32Limit)) + mmio_range(dev, index++, reserved_mmio, + sr->PciResourceMem32Limit - reserved_mmio + 1); } /* |