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authorArthur Heymans <arthur@aheymans.xyz>2024-03-23 15:47:39 +0100
committerMartin L Roth <gaumless@gmail.com>2024-03-28 15:20:43 +0000
commit41eaf2dba315dabb51b5c6a77b083165187ebb18 (patch)
tree2005acb5a43b4c6f9b780ea9c328ba1a9ed28f7e /src/soc/intel/xeon_sp/acpi.c
parentefc615e239004c604a2c907ee36fa21dc6adaf58 (diff)
soc/amd/non_car/memlayout_x86.ld: Top align the code
This does the following: - Top align the bootblock so that the only the memory needed gets used. This might slightly reduce the time the PSP needs to decompress the bootblock in memory - Use a memory directive to assert that the 16bit code is inside the top 64K segment - Use the program counter less. While the BDF linker is happy about running the program counter backwards, LLD is not. There is no downside to this. - Use a symbol rather that the program counter for sections. LLD gets confused when (.) is used along with '<': it places the section at the start of the memory region, rather than at the program counter. Using a variable name works around this. - Use a 'last_byte' section to make sure the first instruction is at 0xfff0. Both the BDF and the LLD linkers seems to work well with this code TEST: Both BFD and LLD are able to link the bootblock Change-Id: I18bdf262f9c358aa01795b11efcb863686edc79c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/acpi.c')
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