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authorJonathan Zhang <jonzhang@fb.com>2020-07-22 12:39:40 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:33:58 +0000
commitd4efb330c1d87ac9f16be4e97b70797dcbe4e3bc (patch)
tree32d2b7d301e5dfb990c62dad7d1d6a322032399b /src/soc/intel/xeon_sp/Kconfig
parente18cdf4d934a24fa0d549d2d2ba5b167cfd8462a (diff)
soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2
CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0. Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed. Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP. TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/Kconfig')
-rw-r--r--src/soc/intel/xeon_sp/Kconfig3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index b410dec37e..cf9ba944e6 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -9,12 +9,14 @@ config XEON_SP_COMMON_BASE
config SOC_INTEL_SKYLAKE_SP
bool
select XEON_SP_COMMON_BASE
+ select PLATFORM_USES_FSP2_0
help
Intel Skylake-SP support
config SOC_INTEL_COOPERLAKE_SP
bool
select XEON_SP_COMMON_BASE
+ select PLATFORM_USES_FSP2_2
help
Intel Cooperlake-SP support
@@ -31,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS
select POSTCAR_CONSOLE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
- select PLATFORM_USES_FSP2_0
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select FSP_T_XIP
select FSP_M_XIP