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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-12 21:05:09 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-20 10:17:56 +0000 |
| commit | 695dd2977bb04024333d52bf561f67a5678845d9 (patch) | |
| tree | cf84bce206ed29a8f43191453168302699efceb5 /src/soc/intel/xeon_sp/Kconfig | |
| parent | 281868e55fb45c093a3342d7581f89e4a65548a6 (diff) | |
soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
This makes coreboot more robust as it does not need to rely on syncing
values set by FSP and coreboot.
Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47533
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/Kconfig')
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3d3e8037db..5c7a667d2f 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_P2SB select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS |