diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-16 22:46:57 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-03-26 02:06:45 +0000 |
| commit | 662da6cf7b181ea2787ba001d9cbb6d41916abec (patch) | |
| tree | 63a95b276913110c423c566db78b856650582ad3 /src/soc/intel/xeon_sp/Kconfig | |
| parent | a1b15172d7f0303e8a1fe147a778d73d4dc26b1a (diff) | |
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.
This is a preparation for future work that will enable next
generation server CPU.
TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/Kconfig')
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 37 |
1 files changed, 11 insertions, 26 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 1f015b15a3..223329d79d 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -13,14 +13,20 @@ ## GNU General Public License for more details. ## -config SOC_INTEL_XEON_SP +source "src/soc/intel/xeon_sp/skx/Kconfig" + +config XEON_SP_COMMON_BASE + bool + +config SOC_INTEL_SKYLAKE_SP bool + select XEON_SP_COMMON_BASE help - Intel Xeon SP support + Intel Skylake-SP support -if SOC_INTEL_XEON_SP +if XEON_SP_COMMON_BASE -config CPU_SPECIFIC_OPTIONS +config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 @@ -54,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_CAR config MAINBOARD_USES_FSP2_0 bool @@ -67,11 +74,6 @@ config USE_FSP2_0_DRIVER select POSTCAR_CONSOLE select POSTCAR_STAGE -config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" - config MAX_SOCKET int default 2 @@ -88,14 +90,6 @@ config PCR_BASE_ADDRESS help This option allows you to select MMIO Base Address of sideband bus. -config DCACHE_RAM_BASE - hex - default 0xfe800000 - -config DCACHE_RAM_SIZE - hex - default 0x200000 - config DCACHE_BSP_STACK_SIZE hex default 0x10000 @@ -104,14 +98,6 @@ config MMCONF_BASE_ADDRESS hex default 0x80000000 -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - config C_ENV_BOOTBLOCK_SIZE hex default 0xC000 @@ -120,5 +106,4 @@ config HEAP_SIZE hex default 0x80000 - endif ## SOC_INTEL_XEON_SP |