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authorAndrey Petrov <anpetrov@fb.com>2020-03-20 12:08:32 -0700
committerAndrey Petrov <anpetrov@fb.com>2020-03-26 18:13:51 +0000
commit2e410757efb824555191d8afd78cf79ab5ba6049 (patch)
treebfd92989b163c3166c7e0911f2cbf37bf2e2b1b1 /src/soc/intel/xeon_sp/Kconfig
parentb75bcc978af50dc409b5356abd33b064029480bb (diff)
soc/intel/xeon_sp: Add basic Cooperlake-SP support
This adds barebones support. What works: * Linux kernel boots fine * SIRQ and PCH interupts work fine (only in IOAPIC mode) * PCH devices are usable What doesn't: * MP init is not there yet, only 1 CPU is up * SMM is not supported * GPIO is not available * All IIO and extended bus numbers enumeration is not yet available * Warm reset flow is untested * MRC cache save/load TEST=boots into Linux Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/Kconfig')
-rw-r--r--src/soc/intel/xeon_sp/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 223329d79d..468cb44c27 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -14,6 +14,7 @@
##
source "src/soc/intel/xeon_sp/skx/Kconfig"
+source "src/soc/intel/xeon_sp/cpx/Kconfig"
config XEON_SP_COMMON_BASE
bool
@@ -24,6 +25,12 @@ config SOC_INTEL_SKYLAKE_SP
help
Intel Skylake-SP support
+config SOC_INTEL_COOPERLAKE_SP
+ bool
+ select XEON_SP_COMMON_BASE
+ help
+ Intel Cooperlake-SP support
+
if XEON_SP_COMMON_BASE
config CPU_SPECIFIC_OPTIONS