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author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-03 12:14:01 -0600 |
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committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-06 04:11:59 +0000 |
commit | 629ddfd265afed7a5198ddbe58aef66297be4c61 (patch) | |
tree | 502f41005f621a0469697ba0a33fdae2133fc297 /src/soc/intel/tigerlake | |
parent | cea4f92e4a2f12d09eef3a8052493786b4e9e18e (diff) |
soc/intel/common: Add virtual wire mapping entries to GPIO communities
Some SoCs may define virtual wire entries for certain GPIOs. This patch
allows SoC code to provide the mappings from GPIO pads to virtual wire
indexes and bits when they are provided. Also a function
`gpio_get_vw_info` is added to return this information.
Change-Id: I87adf0ca06cb5b7969bb2c258d6daebd44bb9748
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52588
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions