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| author | Furquan Shaikh <furquan@google.com> | 2021-08-24 13:42:05 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-09-13 22:42:55 +0000 |
| commit | bee831e95805a963c17a2bba186ce7babd3b92bf (patch) | |
| tree | 05221c2a5bcba5503f6b93d64ef461b5c5cf976c /src/soc/intel/tigerlake | |
| parent | 8edbba4cc48ea42978cd95de015170288b86c3c3 (diff) | |
soc/intel/tgl: Enable USB4 resources based on common Kconfig
Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section
7.2.5.1.5 recommends reserving the following resources for each PCIe
USB4 root port:
- 42 buses
- 194 MiB Non-prefetchable memory
- 448 MiB Prefetchable memory
This change enables reserving of resources for USB4 when mainboard
selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.
This is similar to the change for ADL in commit 8d11cdc6fa
("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources").
Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 00913c7e64..35d8603741 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -287,4 +287,22 @@ config SOC_INTEL_CRASHLOG help Enables CrashLog. +# Intel recommends reserving the following resources per USB4 root port, +# from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 +# - 42 buses +# - 194 MiB Non-prefetchable memory +# - 448 MiB Prefetchable memory +if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config PCIEXP_HOTPLUG_BUSES + default 42 + +config PCIEXP_HOTPLUG_MEM + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + default 0x1c000000 # 448 MiB + +endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + endif |