From bee831e95805a963c17a2bba186ce7babd3b92bf Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 24 Aug 2021 13:42:05 -0700 Subject: soc/intel/tgl: Enable USB4 resources based on common Kconfig Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section 7.2.5.1.5 recommends reserving the following resources for each PCIe USB4 root port: - 42 buses - 194 MiB Non-prefetchable memory - 448 MiB Prefetchable memory This change enables reserving of resources for USB4 when mainboard selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES. This is similar to the change for ADL in commit 8d11cdc6fa ("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources"). Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/Kconfig | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 00913c7e64..35d8603741 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -287,4 +287,22 @@ config SOC_INTEL_CRASHLOG help Enables CrashLog. +# Intel recommends reserving the following resources per USB4 root port, +# from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 +# - 42 buses +# - 194 MiB Non-prefetchable memory +# - 448 MiB Prefetchable memory +if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + +config PCIEXP_HOTPLUG_BUSES + default 42 + +config PCIEXP_HOTPLUG_MEM + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + default 0x1c000000 # 448 MiB + +endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + endif -- cgit v1.2.3