diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2021-08-25 12:30:55 +0100 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-10-01 18:53:28 +0000 |
| commit | f71d8c94eadf269585691a0cebd635b23aa7e21d (patch) | |
| tree | a41f4eaf7222a8b8fade27c9b64a9347a4c8fdf4 /src/soc/intel/tigerlake/uart.c | |
| parent | 7a63f48a5439cffb8b8d5d3ac49fc64ddff0948b (diff) | |
soc/tigerlake: Make IO decode / enable register configurable
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/uart.c')
0 files changed, 0 insertions, 0 deletions