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| author | Yidi Lin <yidi.lin@mediatek.com> | 2021-03-11 17:31:02 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-15 02:27:57 +0000 |
| commit | 2fcbebbbcde4b13df5807d771beeffb0490a9644 (patch) | |
| tree | acdf1c1bd3bfb1dead798cee3eba0ba373152576 /src/soc/intel/tigerlake/spd/ddr4-spd-6.hex | |
| parent | 50c667de524339bb839de71ce0e785a1693d5de3 (diff) | |
mb/google/asurada: revise PMIC and RTC initialization
Move the initialization from bootblock to romstage for following reasons:
- Follow MT8183 initialization sequence.
- PMIC and RTC functions are only called after verstage.
- Reduce bootblock size.
- PMIC initialization setting is complex and may need to be changed by
an RW firmware update.
TEST=boot to kernel successfully
Change-Id: I3e4c3f918639590ffc73076450235771d06aae91
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/spd/ddr4-spd-6.hex')
0 files changed, 0 insertions, 0 deletions